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nileshkale123nileshkale123
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feat(esp_hw_support): Enabled support for memory region protection for H21
This commit enabled CPU region protection for ESP32H21. This alos updated strture for ESP32C6 and ESP32H2.
1 parent 29ea09f commit d4167fe

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5 files changed

+338
-127
lines changed

5 files changed

+338
-127
lines changed

‎components/esp_hw_support/port/esp32c6/cpu_region_protect.c‎

Lines changed: 33 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -142,27 +142,27 @@ void esp_cpu_configure_region_protection(void)
142142
// Anti-FI check that cpu is really in ocd mode
143143
ESP_FAULT_ASSERT(esp_cpu_dbgr_is_attached());
144144

145-
// 5. IRAM and DRAM
146-
const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IRAM_LOW, SOC_IRAM_HIGH);
147-
PMP_ENTRY_SET(5, pmpaddr5, PMP_NAPOT | RWX);
145+
// 3. IRAM and DRAM
146+
const uint32_t pmpaddr3 = PMPADDR_NAPOT(SOC_IRAM_LOW, SOC_IRAM_HIGH);
147+
PMP_ENTRY_SET(3, pmpaddr3, PMP_NAPOT | RWX);
148148
_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
149149
} else {
150150
#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
151151
extern int _iram_text_end;
152-
// 5. IRAM and DRAM
152+
// 3. IRAM and DRAM
153153
/* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
154154
* Bootloader might have given extra permissions and those won't be cleared
155155
*/
156+
PMP_ENTRY_CFG_RESET(3);
157+
PMP_ENTRY_CFG_RESET(4);
156158
PMP_ENTRY_CFG_RESET(5);
157-
PMP_ENTRY_CFG_RESET(6);
158-
PMP_ENTRY_CFG_RESET(7);
159-
PMP_ENTRY_SET(5, SOC_IRAM_LOW, NONE);
160-
PMP_ENTRY_SET(6, (int)&_iram_text_end, PMP_TOR | RX);
161-
PMP_ENTRY_SET(7, SOC_DRAM_HIGH, PMP_TOR | RW);
159+
PMP_ENTRY_SET(3, SOC_IRAM_LOW, NONE);
160+
PMP_ENTRY_SET(4, (int)&_iram_text_end, PMP_TOR | RX);
161+
PMP_ENTRY_SET(5, SOC_DRAM_HIGH, PMP_TOR | RW);
162162
#else
163-
// 5. IRAM and DRAM
164-
const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IRAM_LOW, SOC_IRAM_HIGH);
165-
PMP_ENTRY_SET(5, pmpaddr5, PMP_NAPOT | CONDITIONAL_RWX);
163+
// 3. IRAM and DRAM
164+
const uint32_t pmpaddr3 = PMPADDR_NAPOT(SOC_IRAM_LOW, SOC_IRAM_HIGH);
165+
PMP_ENTRY_SET(3, pmpaddr3, PMP_NAPOT | CONDITIONAL_RWX);
166166
_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
167167
#endif
168168
}
@@ -175,49 +175,48 @@ void esp_cpu_configure_region_protection(void)
175175
const uint32_t drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
176176

177177
// 4. I_Cache / D_Cache (flash)
178+
PMP_ENTRY_CFG_RESET(6);
179+
PMP_ENTRY_CFG_RESET(7);
178180
PMP_ENTRY_CFG_RESET(8);
179-
PMP_ENTRY_CFG_RESET(9);
180-
PMP_ENTRY_CFG_RESET(10);
181-
PMP_ENTRY_SET(8, SOC_IROM_LOW, NONE);
182-
PMP_ENTRY_SET(9, irom_resv_end, PMP_TOR | RX);
183-
PMP_ENTRY_SET(10, drom_resv_end, PMP_TOR | R);
181+
PMP_ENTRY_SET(6, SOC_IROM_LOW, NONE);
182+
PMP_ENTRY_SET(7, irom_resv_end, PMP_TOR | RX);
183+
PMP_ENTRY_SET(8, drom_resv_end, PMP_TOR | R);
184184
#else
185185
// 4. I_Cache / D_Cache (flash)
186-
const uint32_t pmpaddr8 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
187-
PMP_ENTRY_SET(8, pmpaddr8, PMP_NAPOT | CONDITIONAL_RX);
186+
const uint32_t pmpaddr6 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
187+
PMP_ENTRY_SET(6, pmpaddr6, PMP_NAPOT | CONDITIONAL_RX);
188188
_Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I/D_Cache region");
189189
#endif
190190

191-
// 6. LP memory
191+
// 5. LP memory
192192
#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
193193
extern int _rtc_text_start;
194194
extern int _rtc_text_end;
195195
/* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
196196
* Bootloader might have given extra permissions and those won't be cleared
197197
*/
198+
PMP_ENTRY_CFG_RESET(9);
199+
PMP_ENTRY_CFG_RESET(10);
198200
PMP_ENTRY_CFG_RESET(11);
199201
PMP_ENTRY_CFG_RESET(12);
200-
PMP_ENTRY_CFG_RESET(13);
201-
PMP_ENTRY_CFG_RESET(14);
202-
PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW, NONE);
202+
PMP_ENTRY_SET(9, SOC_RTC_IRAM_LOW, NONE);
203203

204204
// First part of LP mem is reserved for ULP coprocessor
205205
#if CONFIG_ESP_SYSTEM_PMP_LP_CORE_RESERVE_MEM_EXECUTABLE
206-
PMP_ENTRY_SET(12, (int)&_rtc_text_start, PMP_TOR | RWX);
206+
PMP_ENTRY_SET(10, (int)&_rtc_text_start, PMP_TOR | RWX);
207207
#else
208-
PMP_ENTRY_SET(12, (int)&_rtc_text_start, PMP_TOR | RW);
208+
PMP_ENTRY_SET(10, (int)&_rtc_text_start, PMP_TOR | RW);
209209
#endif
210-
PMP_ENTRY_SET(13, (int)&_rtc_text_end, PMP_TOR | RX);
211-
PMP_ENTRY_SET(14, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
210+
PMP_ENTRY_SET(11, (int)&_rtc_text_end, PMP_TOR | RX);
211+
PMP_ENTRY_SET(12, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
212212
#else
213-
const uint32_t pmpaddr11 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
214-
PMP_ENTRY_SET(11, pmpaddr11, PMP_NAPOT | CONDITIONAL_RWX);
213+
const uint32_t pmpaddr9 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
214+
PMP_ENTRY_SET(9, pmpaddr9, PMP_NAPOT | CONDITIONAL_RWX);
215215
_Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
216216
#endif
217217

218-
219-
// 7. Peripheral addresses
220-
const uint32_t pmpaddr15 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
221-
PMP_ENTRY_SET(15, pmpaddr15, PMP_NAPOT | RW);
218+
// 6. Peripheral addresses
219+
const uint32_t pmpaddr13 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
220+
PMP_ENTRY_SET(13, pmpaddr13, PMP_NAPOT | RW);
222221
_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
223222
}

‎components/esp_hw_support/port/esp32h2/cpu_region_protect.c‎

Lines changed: 37 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -129,36 +129,36 @@ void esp_cpu_configure_region_protection(void)
129129
PMP_ENTRY_SET(0, pmpaddr0, PMP_NAPOT | RWX);
130130
_Static_assert(SOC_CPU_SUBSYSTEM_LOW < SOC_CPU_SUBSYSTEM_HIGH, "Invalid CPU subsystem region");
131131

132-
// 2.1 I/D-ROM
133-
PMP_ENTRY_SET(1, SOC_IROM_MASK_LOW, NONE);
134-
PMP_ENTRY_SET(2, SOC_IROM_MASK_HIGH, PMP_TOR | RX);
132+
// 2. I/D-ROM
133+
const uint32_t pmpaddr1 = PMPADDR_NAPOT(SOC_IROM_MASK_LOW, SOC_IROM_MASK_HIGH);
134+
PMP_ENTRY_SET(1, pmpaddr1, PMP_NAPOT | RX);
135135
_Static_assert(SOC_IROM_MASK_LOW < SOC_IROM_MASK_HIGH, "Invalid I/D-ROM region");
136136

137137
if (esp_cpu_dbgr_is_attached()) {
138138
// Anti-FI check that cpu is really in ocd mode
139139
ESP_FAULT_ASSERT(esp_cpu_dbgr_is_attached());
140140

141-
// 5. IRAM and DRAM
142-
PMP_ENTRY_SET(5, SOC_IRAM_LOW, NONE);
143-
PMP_ENTRY_SET(6, SOC_IRAM_HIGH, PMP_TOR | RWX);
141+
// 3. IRAM and DRAM
142+
PMP_ENTRY_SET(2, SOC_IRAM_LOW, NONE);
143+
PMP_ENTRY_SET(3, SOC_IRAM_HIGH, PMP_TOR | RWX);
144144
_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
145145
} else {
146146
#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
147147
extern int _iram_text_end;
148-
// 5. IRAM and DRAM
148+
// 3. IRAM and DRAM
149149
/* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
150150
* Bootloader might have given extra permissions and those won't be cleared
151151
*/
152-
PMP_ENTRY_CFG_RESET(5);
153-
PMP_ENTRY_CFG_RESET(6);
154-
PMP_ENTRY_CFG_RESET(7);
155-
PMP_ENTRY_SET(5, SOC_IRAM_LOW, NONE);
156-
PMP_ENTRY_SET(6, (int)&_iram_text_end, PMP_TOR | RX);
157-
PMP_ENTRY_SET(7, SOC_DRAM_HIGH, PMP_TOR | RW);
152+
PMP_ENTRY_CFG_RESET(2);
153+
PMP_ENTRY_CFG_RESET(3);
154+
PMP_ENTRY_CFG_RESET(4);
155+
PMP_ENTRY_SET(2, SOC_IRAM_LOW, NONE);
156+
PMP_ENTRY_SET(3, (int)&_iram_text_end, PMP_TOR | RX);
157+
PMP_ENTRY_SET(4, SOC_DRAM_HIGH, PMP_TOR | RW);
158158
#else
159-
// 5. IRAM and DRAM
160-
PMP_ENTRY_SET(5, SOC_IRAM_LOW, CONDITIONAL_NONE);
161-
PMP_ENTRY_SET(6, SOC_IRAM_HIGH, PMP_TOR | CONDITIONAL_RWX);
159+
// 3. IRAM and DRAM
160+
PMP_ENTRY_SET(2, SOC_IRAM_LOW, CONDITIONAL_NONE);
161+
PMP_ENTRY_SET(3, SOC_IRAM_HIGH, PMP_TOR | CONDITIONAL_RWX);
162162
_Static_assert(SOC_IRAM_LOW < SOC_IRAM_HIGH, "Invalid RAM region");
163163
#endif
164164
}
@@ -171,39 +171,40 @@ void esp_cpu_configure_region_protection(void)
171171
const uint32_t drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
172172

173173
// 4. I_Cache / D_Cache (flash)
174-
PMP_ENTRY_CFG_RESET(8);
175-
PMP_ENTRY_CFG_RESET(9);
176-
PMP_ENTRY_CFG_RESET(10);
177-
PMP_ENTRY_SET(8, SOC_IROM_LOW, NONE);
178-
PMP_ENTRY_SET(9, irom_resv_end, PMP_TOR | RX);
179-
PMP_ENTRY_SET(10, drom_resv_end, PMP_TOR | R);
174+
PMP_ENTRY_CFG_RESET(5);
175+
PMP_ENTRY_CFG_RESET(6);
176+
PMP_ENTRY_CFG_RESET(7);
177+
PMP_ENTRY_SET(5, SOC_IROM_LOW, NONE);
178+
PMP_ENTRY_SET(6, irom_resv_end, PMP_TOR | RX);
179+
PMP_ENTRY_SET(7, drom_resv_end, PMP_TOR | R);
180180
#else
181181
// 4. I_Cache / D_Cache (flash)
182-
const uint32_t pmpaddr8 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
183-
PMP_ENTRY_SET(8, pmpaddr8, PMP_NAPOT | CONDITIONAL_RX);
182+
const uint32_t pmpaddr5 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
183+
PMP_ENTRY_SET(5, pmpaddr5, PMP_NAPOT | CONDITIONAL_RX);
184184
_Static_assert(SOC_IROM_LOW < SOC_IROM_HIGH, "Invalid I/D_Cache region");
185185
#endif
186186

187-
// 6. LP memory
187+
// 5. LP memory
188188
#if CONFIG_ESP_SYSTEM_PMP_IDRAM_SPLIT && !BOOTLOADER_BUILD
189189
extern int _rtc_text_end;
190190
/* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
191191
* Bootloader might have given extra permissions and those won't be cleared
192192
*/
193-
PMP_ENTRY_CFG_RESET(11);
194-
PMP_ENTRY_CFG_RESET(12);
195-
PMP_ENTRY_CFG_RESET(13);
196-
PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW, NONE);
197-
PMP_ENTRY_SET(12, (int)&_rtc_text_end, PMP_TOR | RX);
198-
PMP_ENTRY_SET(13, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
193+
PMP_ENTRY_CFG_RESET(8);
194+
PMP_ENTRY_CFG_RESET(9);
195+
PMP_ENTRY_CFG_RESET(10);
196+
PMP_ENTRY_SET(8, SOC_RTC_IRAM_LOW, NONE);
197+
PMP_ENTRY_SET(9, (int)&_rtc_text_end, PMP_TOR | RX);
198+
PMP_ENTRY_SET(10, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
199199
#else
200-
const uint32_t pmpaddr11 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
201-
PMP_ENTRY_SET(11, pmpaddr11, PMP_NAPOT | CONDITIONAL_RWX);
200+
const uint32_t pmpaddr8 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
201+
PMP_ENTRY_SET(8, pmpaddr8, PMP_NAPOT | CONDITIONAL_RWX);
202202
_Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
203203
#endif
204204

205-
// 7. Peripheral addresses
206-
const uint32_t pmpaddr14 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
207-
PMP_ENTRY_SET(14, pmpaddr14, PMP_NAPOT | RW);
205+
// 6. Peripheral addresses
206+
PMP_ENTRY_CFG_RESET(11);
207+
const uint32_t pmpaddr11 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
208+
PMP_ENTRY_SET(11, pmpaddr11, PMP_NAPOT | RW);
208209
_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
209210
}

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