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refactor(esp_hw_support): seperate sleep modem state support for each target
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5 files changed

+275
-163
lines changed

5 files changed

+275
-163
lines changed

‎components/esp_hw_support/include/esp_private/sleep_modem.h‎

Lines changed: 24 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -120,7 +120,7 @@ bool modem_domain_pd_allowed(void);
120120
uint32_t sleep_modem_reject_triggers(void);
121121

122122
/**
123-
* @brief Configure the parameters of the modem subsytem during the sleep process
123+
* @brief Configure the parameters of the modem subsystem during the sleep process
124124
*
125125
* In light sleep mode, the wake-up early time of the WiFi module and the TBTT
126126
* interrupt early time (trigger enabling RF) are determined by the maximum and
@@ -132,7 +132,7 @@ uint32_t sleep_modem_reject_triggers(void);
132132
*
133133
* @param max_freq_mhz the maximum frequency of system
134134
* @param min_freq_mhz the minimum frequency of system
135-
* @param light_sleep_enable ture or false for enable or disable light sleep mode, respectively
135+
* @param light_sleep_enable true or false for enable or disable light sleep mode, respectively
136136
*
137137
* @return
138138
* - ESP_OK on success
@@ -225,6 +225,27 @@ void sleep_modem_wifi_modem_state_deinit(void);
225225
* - false not skip light sleep
226226
*/
227227
bool sleep_modem_wifi_modem_state_skip_light_sleep(void);
228+
229+
/**
230+
* @brief Function to initialize and create the modem state phy link
231+
* @param link_head the pointer that point to the head of the created phy link
232+
* @return
233+
* - ESP_OK on success
234+
* - ESP_ERR_NO_MEM if no memory for link
235+
* - ESP_ERR_INVALID_ARG if value is out of range
236+
* - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
237+
*/
238+
esp_err_t sleep_modem_state_phy_link_init(void **link_head);
239+
240+
/**
241+
* @brief Function to destroy and de-initialize modem state phy link
242+
* @param link_head the phy link head will be destroyed
243+
* @return
244+
* - ESP_OK on success
245+
* - ESP_ERR_INVALID_ARG if value is out of range
246+
* - ESP_ERR_INVALID_STATE if the phy module retention state is invalid
247+
*/
248+
esp_err_t sleep_modem_state_phy_link_deinit(void *link_head);
228249
#endif
229250

230251
#ifdef __cplusplus

‎components/esp_hw_support/lowpower/CMakeLists.txt‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -24,6 +24,10 @@ if((CONFIG_SOC_PM_SUPPORT_MODEM_PD OR CONFIG_SOC_PM_SUPPORT_TOP_PD) AND CONFIG_S
2424
list(APPEND srcs "port/${target}/sleep_clock.c")
2525
endif()
2626

27+
if(CONFIG_SOC_PM_SUPPORT_PMU_MODEM_STATE)
28+
list(APPEND srcs "port/${target}/sleep_modem_state.c")
29+
endif()
30+
2731
add_prefix(srcs "${CMAKE_CURRENT_LIST_DIR}/" "${srcs}")
2832

2933
target_sources(${COMPONENT_LIB} PRIVATE "${srcs}")

‎components/esp_hw_support/lowpower/port/esp32c5/sleep_modem_state.c‎

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,120 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include "esp_log.h"
7+
#include "esp_check.h"
8+
9+
#include "soc/soc_caps.h"
10+
#include "soc/i2c_ana_mst_reg.h"
11+
#include "soc/pmu_reg.h"
12+
13+
#include "modem/modem_syscon_reg.h"
14+
#include "modem/modem_lpcon_reg.h"
15+
16+
#include "esp_private/sleep_modem.h"
17+
#include "esp_private/sleep_retention.h"
18+
19+
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
20+
21+
#define SARADC_TSENS_REG (0x6000e058)
22+
#define SARADC_TSENS_PU (BIT(22))
23+
#define PMU_RF_PWR_REG (0x600b0158)
24+
25+
#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a001c)
26+
#define FECOEX_SET_CHAN_EN (BIT(17))
27+
#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a0028)
28+
#define FECOEX_SET_CHAN_DONE (BIT(8))
29+
#define FECOEX_AGC_CONF_REG (0x600a7030)
30+
#define FECOEX_AGC_DIS (BIT(29))
31+
32+
#define WDEVTXQ_BLOCK (0x600A4ca8)
33+
#define WDEV_RXBLOCK (BIT(12))
34+
#define MODEM_FE_DATA_BASE (0x600a0400)
35+
#define MODEM_FE_CTRL_BASE (0x600a0800)
36+
37+
static __attribute__((unused)) const char *TAG = "sleep";
38+
39+
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
40+
static esp_err_t sleep_modem_state_phy_wifi_init(void *arg)
41+
{
42+
#define WIFIMAC_ENTRY() (BIT(SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC))
43+
44+
static sleep_retention_entries_config_t wifi_modem_config[] = {
45+
[0] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), .owner = WIFIMAC_ENTRY() }, /* I2C MST enable */
46+
47+
/* PMU or software to trigger enable RF PHY */
48+
[1] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration enable */
49+
[2] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), PMU_RF_PWR_REG, 0xf3800000, 0xf3800000, 1, 0), .owner = WIFIMAC_ENTRY() },
50+
[3] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0), .owner = WIFIMAC_ENTRY() },
51+
[4] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0), .owner = WIFIMAC_ENTRY() },
52+
[5] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0), .owner = WIFIMAC_ENTRY() },
53+
[6] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() },
54+
[7] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x07), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 1, 0), .owner = WIFIMAC_ENTRY() },
55+
[8] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0), .owner = WIFIMAC_ENTRY() },
56+
[9] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0), .owner = WIFIMAC_ENTRY() },
57+
[10] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0), .owner = WIFIMAC_ENTRY() },
58+
59+
/* PMU to trigger enable RXBLOCK */
60+
[11] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0), .owner = WIFIMAC_ENTRY() },
61+
62+
/* PMU or software to trigger disable RF PHY */
63+
[12] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0c), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1), .owner = WIFIMAC_ENTRY() },
64+
[13] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0d), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1), .owner = WIFIMAC_ENTRY() },
65+
[14] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x20000, 0, 1), .owner = WIFIMAC_ENTRY() },
66+
[15] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 1), .owner = WIFIMAC_ENTRY() },
67+
[16] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x10), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 1), .owner = WIFIMAC_ENTRY() },
68+
[17] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), SARADC_TSENS_REG, 0, 0x400000, 0, 1), .owner = WIFIMAC_ENTRY() },
69+
[18] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), PMU_RF_PWR_REG, 0, 0xf3800000, 0, 1), .owner = WIFIMAC_ENTRY() },
70+
[19] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), .owner = WIFIMAC_ENTRY() }, /* BBPLL calibration disable */
71+
72+
[20] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), .owner = WIFIMAC_ENTRY() }, /* I2C MST disable */
73+
74+
/* PMU to trigger disable RXBLOCK */
75+
[21] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x15), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() },
76+
[22] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x16), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1), .owner = WIFIMAC_ENTRY() },
77+
[23] = { .config = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1), .owner = WIFIMAC_ENTRY() },
78+
79+
[24] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0), .owner = WIFIMAC_ENTRY() },
80+
[25] = { .config = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1), .owner = WIFIMAC_ENTRY() }
81+
};
82+
extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
83+
wifi_modem_config[4].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
84+
wifi_modem_config[15].config.write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
85+
esp_err_t err = sleep_retention_entries_create(wifi_modem_config, ARRAY_SIZE(wifi_modem_config), 7, SLEEP_RETENTION_MODULE_MODEM_PHY);
86+
ESP_RETURN_ON_ERROR(err, TAG, "failed to allocate modem phy link for wifi modem state");
87+
return ESP_OK;
88+
}
89+
#endif
90+
91+
esp_err_t sleep_modem_state_phy_link_init(void **link_head)
92+
{
93+
esp_err_t err = ESP_OK;
94+
95+
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
96+
sleep_retention_module_init_param_t init_param = { .cbs = { .create = { .handle = sleep_modem_state_phy_wifi_init, .arg = NULL } } };
97+
err = sleep_retention_module_init(SLEEP_RETENTION_MODULE_MODEM_PHY, &init_param);
98+
if (err == ESP_OK) {
99+
err = sleep_retention_module_allocate(SLEEP_RETENTION_MODULE_MODEM_PHY);
100+
if (err == ESP_OK) {
101+
*link_head = sleep_retention_find_link_by_id(REGDMA_PHY_LINK(0x00));
102+
}
103+
}
104+
#endif
105+
return err;
106+
}
107+
108+
esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
109+
{
110+
esp_err_t err = ESP_OK;
111+
#if SOC_PM_PAU_REGDMA_LINK_IDX_WIFIMAC
112+
err = sleep_retention_module_free(SLEEP_RETENTION_MODULE_MODEM_PHY);
113+
if (err == ESP_OK) {
114+
sleep_retention_module_deinit(SLEEP_RETENTION_MODULE_MODEM_PHY);
115+
}
116+
#endif
117+
return err;
118+
}
119+
120+
#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */

‎components/esp_hw_support/lowpower/port/esp32c6/sleep_modem_state.c‎

Lines changed: 122 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,122 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#include "soc/soc_caps.h"
7+
#include "soc/i2c_ana_mst_reg.h"
8+
#include "soc/pmu_reg.h"
9+
10+
#include "modem/modem_syscon_reg.h"
11+
#include "modem/modem_lpcon_reg.h"
12+
13+
#include "esp_private/esp_pau.h"
14+
#include "esp_private/sleep_modem.h"
15+
#include "esp_private/sleep_retention.h"
16+
17+
#if SOC_PM_SUPPORT_PMU_MODEM_STATE
18+
19+
#define SARADC_TSENS_REG (0x6000e058)
20+
#define SARADC_TSENS_PU (BIT(22))
21+
#define PMU_RF_PWR_REG (0x600b0154)
22+
23+
#define FECOEX_SET_FREQ_SET_CHAN_REG (0x600a00c0)
24+
#define FECOEX_SET_CHAN_EN (BIT(14))
25+
#define FECOEX_SET_FREQ_SET_CHAN_ST_REG (0x600a00cc)
26+
#define FECOEX_SET_CHAN_DONE (BIT(8))
27+
#define FECOEX_AGC_CONF_REG (0x600a7030)
28+
#define FECOEX_AGC_DIS (BIT(29))
29+
30+
#define WDEVTXQ_BLOCK (0x600A4ca8)
31+
#define WDEV_RXBLOCK (BIT(12))
32+
#define MODEM_FE_DATA_BASE (0x600a0400)
33+
#define MODEM_FE_CTRL_BASE (0x600a0800)
34+
35+
esp_err_t sleep_modem_state_phy_link_init(void **link_head)
36+
{
37+
esp_err_t err = ESP_OK;
38+
39+
#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
40+
static regdma_link_config_t wifi_modem_config[] = {
41+
[0] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(0), MODEM_FE_DATA_BASE, MODEM_FE_DATA_BASE, 41, 0, 0),
42+
[1] = REGDMA_LINK_CONTINUOUS_INIT(REGDMA_MODEM_FE_LINK(1), MODEM_FE_CTRL_BASE, MODEM_FE_CTRL_BASE, 87, 0, 0),
43+
44+
[2] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x00), MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN, MODEM_LPCON_CLK_I2C_MST_EN_M, 1, 0), /* I2C MST enable */
45+
[3] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x01), MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M, MODEM_LPCON_CLK_I2C_MST_SEL_160M_M, 1, 0), /* I2C MST sel 160m enable */
46+
47+
/* PMU or software to trigger enable RF PHY */
48+
[4] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x02), I2C_ANA_MST_ANA_CONF0_REG, 0x8, 0xc, 1, 0), /* BBPLL calibration enable */
49+
[5] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x03), PMU_RF_PWR_REG, 0xf0000000, 0xf0000000, 1, 0),
50+
[6] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x04), SARADC_TSENS_REG, SARADC_TSENS_PU, 0x400000, 1, 0),
51+
[7] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x05), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 1, 0),
52+
[8] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x06), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 1, 0),
53+
[9] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x07), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 1, 0),
54+
[10] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x08), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 1, 0),
55+
[11] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x09), FECOEX_SET_FREQ_SET_CHAN_REG, FECOEX_SET_CHAN_EN, 0x4000, 1, 0),
56+
[12] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0a), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x4000, 1, 0),
57+
[13] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0b), PMU_DATE_REG, ~FECOEX_SET_CHAN_DONE, 0x100, 1, 0),
58+
[14] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0c), PMU_DATE_REG, ~FECOEX_SET_CHAN_DONE, 0x100, 1, 0),
59+
[15] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x0d), FECOEX_SET_FREQ_SET_CHAN_ST_REG, FECOEX_SET_CHAN_DONE, 0x100, 1, 0),
60+
[16] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0e), MODEM_SYSCON_WIFI_BB_CFG_REG, BIT(1), 0x2, 1, 0),
61+
[17] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x0f), FECOEX_AGC_CONF_REG, 0, 0x20000000, 1, 0),
62+
63+
/* PMU to trigger enable RXBLOCK */
64+
[18] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x10), WDEVTXQ_BLOCK, 0, 0x1000, 1, 0),
65+
66+
/* PMU or software to trigger disable RF PHY */
67+
[19] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x11), FECOEX_AGC_CONF_REG, FECOEX_AGC_DIS, 0x20000000, 0, 1),
68+
[20] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x12), MODEM_SYSCON_WIFI_BB_CFG_REG, 0, 0x2, 0, 1),
69+
[21] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x13), FECOEX_SET_FREQ_SET_CHAN_REG, 0, 0x4000, 0, 1),
70+
[22] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x14), I2C_ANA_MST_I2C_BURST_CONF_REG, 0, 0xffffffff, 0, 1),
71+
[23] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x15), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
72+
[24] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x16), PMU_DATE_REG, ~I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
73+
[25] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x17), I2C_ANA_MST_I2C_BURST_STATUS_REG, I2C_ANA_MST_BURST_DONE, 0x1, 0, 1),
74+
[26] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x18), SARADC_TSENS_REG, 0, 0x400000, 0, 1),
75+
[27] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x19), PMU_RF_PWR_REG, 0, 0xf0000000, 0, 1),
76+
[28] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1a), I2C_ANA_MST_ANA_CONF0_REG, 0x4, 0xc, 0, 1), /* BBPLL calibration disable */
77+
78+
[29] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1b), MODEM_LPCON_CLK_CONF_REG, 0, MODEM_LPCON_CLK_I2C_MST_EN_M, 0, 1), /* I2C MST disable */
79+
80+
/* PMU to trigger disable RXBLOCK */
81+
[30] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1c), PMU_DATE_REG, ~0, 0x6000, 0, 1),
82+
[31] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1d), PMU_DATE_REG, ~0, 0x6000, 0, 1),
83+
[32] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x1e), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1),
84+
[33] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x1f), WDEVTXQ_BLOCK, WDEV_RXBLOCK, 0x1000, 0, 1),
85+
[34] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x20), PMU_DATE_REG, ~0, 0x6000, 0, 1),
86+
[35] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x21), PMU_DATE_REG, ~0, 0x6000, 0, 1),
87+
[36] = REGDMA_LINK_WAIT_INIT (REGDMA_PHY_LINK(0x22), WDEVTXQ_BLOCK, 0, 0x6000, 0, 1),
88+
89+
[37] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x23), PMU_SLP_WAKEUP_CNTL7_REG, 0x200000, 0xffff0000, 1, 0),
90+
[38] = REGDMA_LINK_WRITE_INIT(REGDMA_PHY_LINK(0x24), PMU_SLP_WAKEUP_CNTL7_REG, 0x9730000, 0xffff0000, 0, 1)
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};
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extern uint32_t phy_ana_i2c_master_burst_rf_onoff(bool on);
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wifi_modem_config[7].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(true);
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wifi_modem_config[22].write_wait.value = phy_ana_i2c_master_burst_rf_onoff(false);
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void *link = NULL;
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for (int i = ARRAY_SIZE(wifi_modem_config) - 1; (err == ESP_OK) && (i >= 0); i--) {
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void *next = regdma_link_init_safe(&wifi_modem_config[i], false, 0, link);
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if (next) {
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link = next;
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} else {
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regdma_link_destroy(link, 0);
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err = ESP_ERR_NO_MEM;
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}
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}
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if (err == ESP_OK) {
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pau_regdma_set_modem_link_addr(link);
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*link_head = link;
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}
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#endif
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return err;
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}
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esp_err_t sleep_modem_state_phy_link_deinit(void *link_head)
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{
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#if SOC_PM_PAU_REGDMA_LINK_WIFIMAC
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regdma_link_destroy(link_head, 0);
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#endif
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return ESP_OK;
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}
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#endif /* SOC_PM_SUPPORT_PMU_MODEM_STATE */

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