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Harshal5Harshal5
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Merge branch 'feat/some_xip_psram_related_optimisations_and_fixes' into 'master'
feat(esp_psram): Fix late PSRAM init and add some wasted XIP PSRAM memory in heap Closes IDF-11463 and IDF-10555 See merge request espressif/esp-idf!37116
2 parents 9e95a68 + 003b54e commit d898c23

34 files changed

+894
-110
lines changed

‎components/esp_hw_support/port/esp32c5/cpu_region_protect.c‎

Lines changed: 68 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -9,6 +9,9 @@
99
#include "esp_cpu.h"
1010
#include "esp_fault.h"
1111
#include "esp32c5/rom/rom_layout.h"
12+
#if CONFIG_SPIRAM
13+
#include "esp_private/esp_psram_extram.h"
14+
#endif /* CONFIG_SPIRAM */
1215

1316
#ifdef BOOTLOADER_BUILD
1417
// Without L bit set
@@ -26,6 +29,7 @@
2629

2730
#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1))
2831
#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1))
32+
#define ALIGN_UP(addr, align) ((addr) & ~((align) - 1))
2933

3034
static void esp_cpu_configure_invalid_regions(void)
3135
{
@@ -178,15 +182,60 @@ void esp_cpu_configure_region_protection(void)
178182
extern int _instruction_reserved_end;
179183
extern int _rodata_reserved_end;
180184

181-
const uint32_t irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
182-
const uint32_t drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
185+
const uint32_t page_aligned_irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
186+
__attribute__((unused)) const uint32_t page_aligned_drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
183187

184188
PMP_ENTRY_CFG_RESET(6);
189+
PMP_ENTRY_SET(6, SOC_IROM_LOW, NONE);
190+
191+
/**
192+
Virtual space layout:
193+
194+
_________ <- SOC_IROM_LOW
195+
| |
196+
|_______| <- _instruction_reserved_end
197+
|_______| <- page_aligned_irom_resv_end
198+
| |
199+
|_______| <- _rodata_reserved_end
200+
|_______| <- page_aligned_drom_resv_end
201+
| |
202+
| |
203+
| |
204+
|_______| <- page_aligned_drom_resv_end + available_psram_heap
205+
| |
206+
| |
207+
| |
208+
| |
209+
|_______| <- SOC_DROM_HIGH
210+
211+
if CONFIG_SPIRAM_FETCH_INSTRUCTIONS: [_instruction_reserved_end, page_aligned_irom_resv_end) in heap (RW)
212+
if CONFIG_SPIRAM_RODATA: [_rodata_reserved_end, page_aligned_drom_resv_end) in heap (RW)
213+
if CONFIG_SPIRAM: [_rodata_reserved_end, page_aligned_drom_resv_end + available_psram_heap] in heap / reserved for mapping (RW)
214+
*/
215+
185216
PMP_ENTRY_CFG_RESET(7);
186217
PMP_ENTRY_CFG_RESET(8);
187-
PMP_ENTRY_SET(6, SOC_IROM_LOW, NONE);
188-
PMP_ENTRY_SET(7, irom_resv_end, PMP_TOR | RX);
189-
PMP_ENTRY_SET(8, drom_resv_end, PMP_TOR | R);
218+
PMP_ENTRY_CFG_RESET(9);
219+
220+
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
221+
PMP_ENTRY_SET(7, (uint32_t)(&_instruction_reserved_end), PMP_TOR | RX);
222+
PMP_ENTRY_SET(8, page_aligned_irom_resv_end, PMP_TOR | RW);
223+
#else
224+
PMP_ENTRY_SET(7, page_aligned_irom_resv_end, PMP_TOR | RX);
225+
PMP_ENTRY_SET(8, page_aligned_irom_resv_end, NONE);
226+
#endif /* CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */
227+
228+
#if CONFIG_SPIRAM_RODATA && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
229+
PMP_ENTRY_SET(9, (uint32_t)(&_rodata_reserved_end), PMP_TOR | R);
230+
#else
231+
PMP_ENTRY_SET(9, page_aligned_drom_resv_end, PMP_TOR | R);
232+
#endif /* CONFIG_SPIRAM_RODATA && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */
233+
234+
#if CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
235+
size_t available_psram_heap = esp_psram_get_heap_size_to_protect();
236+
PMP_ENTRY_CFG_RESET(10);
237+
PMP_ENTRY_SET(10, ALIGN_UP(page_aligned_drom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW);
238+
#endif /* CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */
190239
#else
191240
const uint32_t pmpaddr6 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
192241
// Add the W attribute in the case of PSRAM
@@ -201,29 +250,31 @@ void esp_cpu_configure_region_protection(void)
201250
/* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
202251
* Bootloader might have given extra permissions and those won't be cleared
203252
*/
204-
PMP_ENTRY_CFG_RESET(9);
205-
PMP_ENTRY_CFG_RESET(10);
206253
PMP_ENTRY_CFG_RESET(11);
207254
PMP_ENTRY_CFG_RESET(12);
208-
PMP_ENTRY_SET(9, SOC_RTC_IRAM_LOW, NONE);
255+
PMP_ENTRY_CFG_RESET(13);
256+
PMP_ENTRY_CFG_RESET(14);
257+
258+
PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW, NONE);
209259

210260
// First part of LP mem is reserved for ULP coprocessor
211261
#if CONFIG_ESP_SYSTEM_PMP_LP_CORE_RESERVE_MEM_EXECUTABLE
212-
PMP_ENTRY_SET(10, (int)&_rtc_text_start, PMP_TOR | RWX);
262+
PMP_ENTRY_SET(12, (int)&_rtc_text_start, PMP_TOR | RWX);
213263
#else
214-
PMP_ENTRY_SET(10, (int)&_rtc_text_start, PMP_TOR | RW);
264+
PMP_ENTRY_SET(12, (int)&_rtc_text_start, PMP_TOR | RW);
215265
#endif
216266

217-
PMP_ENTRY_SET(11, (int)&_rtc_text_end, PMP_TOR | RX);
218-
PMP_ENTRY_SET(12, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
267+
PMP_ENTRY_SET(13, (int)&_rtc_text_end, PMP_TOR | RX);
268+
PMP_ENTRY_SET(14, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
219269
#else
220-
const uint32_t pmpaddr9 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
221-
PMP_ENTRY_SET(9, pmpaddr9, PMP_NAPOT | CONDITIONAL_RWX);
270+
const uint32_t pmpaddr11 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
271+
PMP_ENTRY_SET(11, pmpaddr11, PMP_NAPOT | CONDITIONAL_RWX);
222272
_Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
223273
#endif
224274

225275
// 6. Peripheral addresses
226-
const uint32_t pmpaddr13 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
227-
PMP_ENTRY_SET(13, pmpaddr13, PMP_NAPOT | RW);
276+
PMP_ENTRY_CFG_RESET(15);
277+
const uint32_t pmpaddr15 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
278+
PMP_ENTRY_SET(15, pmpaddr15, PMP_NAPOT | RW);
228279
_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
229280
}

‎components/esp_hw_support/port/esp32c61/cpu_region_protect.c‎

Lines changed: 56 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -10,6 +10,9 @@
1010
#include "esp_cpu.h"
1111
#include "esp_fault.h"
1212
#include "esp32c61/rom/rom_layout.h"
13+
#if CONFIG_SPIRAM
14+
#include "esp_private/esp_psram_extram.h"
15+
#endif /* CONFIG_SPIRAM */
1316

1417
#ifdef BOOTLOADER_BUILD
1518
// Without L bit set
@@ -27,6 +30,7 @@
2730

2831
#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1))
2932
#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1))
33+
#define ALIGN_UP(addr, align) ((addr) & ~((align) - 1))
3034

3135
static void esp_cpu_configure_invalid_regions(void)
3236
{
@@ -172,16 +176,60 @@ void esp_cpu_configure_region_protection(void)
172176
extern int _instruction_reserved_end;
173177
extern int _rodata_reserved_end;
174178

175-
const uint32_t irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
176-
const uint32_t drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
179+
const uint32_t page_aligned_irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
180+
__attribute__((unused)) const uint32_t page_aligned_drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
177181

178182
PMP_ENTRY_CFG_RESET(7);
183+
PMP_ENTRY_SET(7, SOC_IROM_LOW, NONE);
184+
185+
/**
186+
Virtual space layout:
187+
188+
_________ <- SOC_IROM_LOW
189+
| |
190+
|_______| <- _instruction_reserved_end
191+
|_______| <- page_aligned_irom_resv_end
192+
| |
193+
|_______| <- _rodata_reserved_end
194+
|_______| <- page_aligned_drom_resv_end
195+
| |
196+
| |
197+
| |
198+
|_______| <- page_aligned_drom_resv_end + available_psram_heap
199+
| |
200+
| |
201+
| |
202+
| |
203+
|_______| <- SOC_DROM_HIGH
204+
205+
if CONFIG_SPIRAM_FETCH_INSTRUCTIONS: [_instruction_reserved_end, page_aligned_irom_resv_end) in heap (RW)
206+
if CONFIG_SPIRAM_RODATA: [_rodata_reserved_end, page_aligned_drom_resv_end) in heap (RW)
207+
if CONFIG_SPIRAM: [_rodata_reserved_end, page_aligned_drom_resv_end + available_psram_heap] in heap / reserved for mapping (RW)
208+
*/
209+
179210
PMP_ENTRY_CFG_RESET(8);
180211
PMP_ENTRY_CFG_RESET(9);
181212
PMP_ENTRY_CFG_RESET(10);
182-
PMP_ENTRY_SET(7, SOC_IROM_LOW, NONE);
183-
PMP_ENTRY_SET(8, irom_resv_end, PMP_TOR | RX);
184-
PMP_ENTRY_SET(9, drom_resv_end, PMP_TOR | R);
213+
214+
#if CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
215+
PMP_ENTRY_SET(8, (uint32_t)(&_instruction_reserved_end), PMP_TOR | RX);
216+
PMP_ENTRY_SET(9, page_aligned_irom_resv_end, PMP_TOR | RW);
217+
#else
218+
PMP_ENTRY_SET(8, page_aligned_irom_resv_end, PMP_TOR | RX);
219+
PMP_ENTRY_SET(9, page_aligned_irom_resv_end, NONE);
220+
#endif /* CONFIG_SPIRAM_FETCH_INSTRUCTIONS && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */
221+
222+
#if CONFIG_SPIRAM_RODATA && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
223+
PMP_ENTRY_SET(10, (uint32_t)(&_rodata_reserved_end), PMP_TOR | R);
224+
#else
225+
PMP_ENTRY_SET(10, page_aligned_drom_resv_end, PMP_TOR | R);
226+
#endif /* CONFIG_SPIRAM_RODATA && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION*/
227+
228+
#if CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
229+
size_t available_psram_heap = esp_psram_get_heap_size_to_protect();
230+
PMP_ENTRY_CFG_RESET(11);
231+
PMP_ENTRY_SET(11, ALIGN_UP(page_aligned_drom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW);
232+
#endif /* CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */
185233
#else
186234
const uint32_t pmpaddr7 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
187235
// Add the W attribute in the case of PSRAM
@@ -190,7 +238,7 @@ void esp_cpu_configure_region_protection(void)
190238
#endif
191239

192240
// 5. Peripheral addresses
193-
const uint32_t pmpaddr10 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
194-
PMP_ENTRY_SET(10, pmpaddr10, PMP_NAPOT | RW);
241+
const uint32_t pmpaddr12 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
242+
PMP_ENTRY_SET(12, pmpaddr12, PMP_NAPOT | RW);
195243
_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
196244
}

‎components/esp_hw_support/port/esp32p4/cpu_region_protect.c‎

Lines changed: 38 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -11,6 +11,9 @@
1111
#include "esp_fault.h"
1212
#include "hal/cache_ll.h"
1313
#include "riscv/csr.h"
14+
#if CONFIG_SPIRAM
15+
#include "esp_private/esp_psram_extram.h"
16+
#endif /* CONFIG_SPIRAM */
1417

1518
#ifdef BOOTLOADER_BUILD
1619
// Without L bit set
@@ -30,6 +33,7 @@
3033

3134
#define ALIGN_UP_TO_MMU_PAGE_SIZE(addr) (((addr) + (SOC_MMU_PAGE_SIZE) - 1) & ~((SOC_MMU_PAGE_SIZE) - 1))
3235
#define ALIGN_DOWN_TO_MMU_PAGE_SIZE(addr) ((addr) & ~((SOC_MMU_PAGE_SIZE) - 1))
36+
#define ALIGN_UP(addr, align) ((addr) & ~((align) - 1))
3337

3438
static void esp_cpu_configure_invalid_regions(void)
3539
{
@@ -191,16 +195,34 @@ void esp_cpu_configure_region_protection(void)
191195
extern int _instruction_reserved_end;
192196
extern int _rodata_reserved_end;
193197

194-
const uint32_t irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
195-
const uint32_t drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
198+
const uint32_t page_aligned_irom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_instruction_reserved_end));
199+
__attribute__((unused)) const uint32_t page_aligned_drom_resv_end = ALIGN_UP_TO_MMU_PAGE_SIZE((uint32_t)(&_rodata_reserved_end));
196200

197201
// 5. I_Cache / D_Cache (flash)
202+
#if CONFIG_SPIRAM_XIP_FROM_PSRAM && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
203+
// We could have split CONFIG_SPIRAM_XIP_FROM_PSRAM into CONFIG_SPIRAM_FETCH_INSTRUCTIONS and CONFIG_SPIRAM_RODATA
204+
// but we don't have enough PMP entries to do so thus not allowing us finer control over the memory regions
205+
PMP_ENTRY_CFG_RESET(6);
206+
PMP_ENTRY_CFG_RESET(7);
207+
PMP_ENTRY_CFG_RESET(8);
208+
PMP_ENTRY_CFG_RESET(9);
209+
210+
PMP_ENTRY_SET(6, SOC_EXTRAM_LOW, NONE);
211+
PMP_ENTRY_SET(7, (uint32_t)(&_instruction_reserved_end), PMP_TOR | RX);
212+
PMP_ENTRY_SET(8, page_aligned_irom_resv_end, PMP_TOR | RW);
213+
PMP_ENTRY_SET(9, (uint32_t)(&_rodata_reserved_end), PMP_TOR | R);
214+
215+
size_t available_psram_heap = esp_psram_get_heap_size_to_protect();
216+
PMP_ENTRY_CFG_RESET(10);
217+
PMP_ENTRY_SET(10, ALIGN_UP(page_aligned_drom_resv_end + available_psram_heap, SOC_CPU_PMP_REGION_GRANULARITY), PMP_TOR | RW);
218+
#else
198219
PMP_ENTRY_CFG_RESET(6);
199220
PMP_ENTRY_CFG_RESET(7);
200221
PMP_ENTRY_CFG_RESET(8);
201222
PMP_ENTRY_SET(6, SOC_IROM_LOW, NONE);
202-
PMP_ENTRY_SET(7, irom_resv_end, PMP_TOR | RX);
203-
PMP_ENTRY_SET(8, drom_resv_end, PMP_TOR | R);
223+
PMP_ENTRY_SET(7, page_aligned_irom_resv_end, PMP_TOR | RX);
224+
PMP_ENTRY_SET(8, page_aligned_drom_resv_end, PMP_TOR | R);
225+
#endif /* CONFIG_SPIRAM_XIP_FROM_PSRAM && CONFIG_SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION */
204226
#else
205227
// 5. I_Cache / D_Cache (flash)
206228
const uint32_t pmpaddr6 = PMPADDR_NAPOT(SOC_IROM_LOW, SOC_IROM_HIGH);
@@ -215,28 +237,28 @@ void esp_cpu_configure_region_protection(void)
215237
/* Reset the corresponding PMP config because PMP_ENTRY_SET only sets the given bits
216238
* Bootloader might have given extra permissions and those won't be cleared
217239
*/
218-
PMP_ENTRY_CFG_RESET(9);
219-
PMP_ENTRY_CFG_RESET(10);
220240
PMP_ENTRY_CFG_RESET(11);
221241
PMP_ENTRY_CFG_RESET(12);
222-
PMP_ENTRY_SET(9, SOC_RTC_IRAM_LOW, NONE);
242+
PMP_ENTRY_CFG_RESET(13);
243+
PMP_ENTRY_CFG_RESET(14);
244+
PMP_ENTRY_SET(11, SOC_RTC_IRAM_LOW, NONE);
223245
// First part of LP mem is reserved for RTC reserved mem (shared between bootloader and app)
224246
// as well as memory for ULP coprocessor
225247
#if CONFIG_ESP_SYSTEM_PMP_LP_CORE_RESERVE_MEM_EXECUTABLE
226-
PMP_ENTRY_SET(10, (int)&_rtc_text_start, PMP_TOR | RWX);
248+
PMP_ENTRY_SET(12, (int)&_rtc_text_start, PMP_TOR | RWX);
227249
#else
228-
PMP_ENTRY_SET(10, (int)&_rtc_text_start, PMP_TOR | RW);
250+
PMP_ENTRY_SET(12, (int)&_rtc_text_start, PMP_TOR | RW);
229251
#endif
230-
PMP_ENTRY_SET(11, (int)&_rtc_text_end, PMP_TOR | RX);
231-
PMP_ENTRY_SET(12, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
252+
PMP_ENTRY_SET(13, (int)&_rtc_text_end, PMP_TOR | RX);
253+
PMP_ENTRY_SET(14, SOC_RTC_IRAM_HIGH, PMP_TOR | RW);
232254
#else
233-
const uint32_t pmpaddr9 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
234-
PMP_ENTRY_SET(9, pmpaddr9, PMP_NAPOT | CONDITIONAL_RWX);
255+
const uint32_t pmpaddr11 = PMPADDR_NAPOT(SOC_RTC_IRAM_LOW, SOC_RTC_IRAM_HIGH);
256+
PMP_ENTRY_SET(11, pmpaddr11, PMP_NAPOT | CONDITIONAL_RWX);
235257
_Static_assert(SOC_RTC_IRAM_LOW < SOC_RTC_IRAM_HIGH, "Invalid RTC IRAM region");
236258
#endif
237259

238260
// 7. Peripheral addresses
239-
const uint32_t pmpaddr13 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
240-
PMP_ENTRY_SET(13, pmpaddr13, PMP_NAPOT | RW);
261+
const uint32_t pmpaddr15 = PMPADDR_NAPOT(SOC_PERIPHERAL_LOW, SOC_PERIPHERAL_HIGH);
262+
PMP_ENTRY_SET(15, pmpaddr15, PMP_NAPOT | RW);
241263
_Static_assert(SOC_PERIPHERAL_LOW < SOC_PERIPHERAL_HIGH, "Invalid peripheral region");
242264
}

‎components/esp_psram/Kconfig.spiram.common‎

Lines changed: 39 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,18 +2,53 @@
22
#
33
# sourced into the "SPIRAM config" submenu for a specific chip.
44

5+
config SPIRAM_BOOT_HW_INIT
6+
bool "Initialise the PSRAM related hardware"
7+
depends on SPIRAM
8+
default "y" if SPIRAM
9+
help
10+
If this is enabled, the PSRAM hardware will be initialized during startup.
11+
Enabling this config does not ensure make sure the availability of the PSRAM for usage,
12+
but just initialises the PSRAM hardware.
13+
This is necessary to configure PSRAM memory protection during the boot up.
14+
515
config SPIRAM_BOOT_INIT
6-
bool "Initialize SPI RAM during startup"
16+
bool "Initialize PSRAM during startup, including the hardware and memory related configurations"
717
default "y"
18+
depends on SPIRAM_BOOT_HW_INIT
819
help
9-
If this is enabled, the SPI RAM will be enabled during initial boot. Unless you
20+
If this is enabled, the PSRAM will be enabled during initial boot. Unless you
1021
have specific requirements, you'll want to leave this enabled so memory allocated
11-
during boot-up can also be placed in SPI RAM.
22+
during boot-up can also be placed in PSRAM.
23+
24+
config SPIRAM_PRE_CONFIGURE_MEMORY_PROTECTION
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bool "Pre-configure memory protection for PSRAM"
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default y if SPIRAM_BOOT_INIT
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default n
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depends on SPIRAM
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help
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If this is enabled, the PSRAM will be pre-configured for memory protection during initial boot.
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This configuration takes into consideration the PSRAM memory configurations that are performed
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by ESP-IDF's default PSRAM initialization function, esp_psram_init().
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Thus, the config is enabled by default when SPIRAM_BOOT_INIT is enabled,
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because the function esp_psram_init() would be called in the startup code.
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In case you wish to disable SPIRAM_BOOT_INIT just for delaying the PSRAM initialization and plan
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to use the ESP-IDF's default PSRAM initialization function, esp_psram_init() in the application code,
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you should still enable this config to enable memory protection for the PSRAM.
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Note that enabling this config also considers that the rest of the PSRAM memory that is left after
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the memory configurations are performed by esp_psram_init(), can be allocated to the heap using the function
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esp_psram_extram_add_to_heap_allocator(), thus configures this region with heap memory protection (RW).
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As an advanced usage, if you plan to initialize the PSRAM memory regions manually by yourself without
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using the function esp_psram_init(), you should disable this config to avoid any memory protection and
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usage conflicts.
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config SPIRAM_IGNORE_NOTFOUND
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bool "Ignore PSRAM when not found"
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default "n"
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depends on SPIRAM_BOOT_INIT && !SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY && !SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
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depends on SPIRAM_BOOT_HW_INIT && !SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY && !SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY
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help
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Normally, if psram initialization is enabled during compile time but not found at runtime, it
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is seen as an error making the CPU panic. If this is enabled, booting will complete

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