fix(soc): Fixed ECDSA register compatibility

Author: AdityaHPatwardhan

components/esp_security/src/init.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -42,6 +42,10 @@ ESP_SYSTEM_INIT_FN(esp_security_init, SECONDARY, BIT(0), 103)
     esp_crypto_dpa_protection_startup();
 #endif
 
+#if SOC_ECDSA_REGISTER_INCOMPATIBILITY_ACROSS_REV
+    ecdsa_compatible_mem_reg_addr_init();
+#endif
+
 #if CONFIG_ESP_CRYPTO_FORCE_ECC_CONSTANT_TIME_POINT_MUL
     bool force_constant_time = true;
 #if CONFIG_IDF_TARGET_ESP32H2

components/hal/ecdsa_hal.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -137,11 +137,15 @@ void ecdsa_hal_gen_signature(ecdsa_hal_config_t *conf, const uint8_t *hash,
     configure_ecdsa_periph(conf);
 
 #if CONFIG_HAL_ECDSA_GEN_SIG_CM
+#if CONFIG_IDF_TARGET_ESP32H2
     if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102)) {
         ecdsa_hal_gen_signature_with_countermeasure(hash, r_out, s_out, len);
     } else {
         ecdsa_hal_gen_signature_inner(hash, r_out, s_out, len);
     }
+#else
+    ecdsa_hal_gen_signature_with_countermeasure(hash, r_out, s_out, len);
+#endif
 #else /* CONFIG_HAL_ECDSA_GEN_SIG_CM */
     ecdsa_hal_gen_signature_inner(hash, r_out, s_out, len);
 #endif /* !CONFIG_HAL_ECDSA_GEN_SIG_CM */

components/hal/esp32h2/include/hal/ecc_ll.h

@@ -13,7 +13,7 @@
 #include "soc/pcr_struct.h"
 #include "soc/pcr_reg.h"
 #include "soc/chip_revision.h"
-#include "hal/efuse_ll.h"
+#include "hal/efuse_hal.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -216,7 +216,7 @@ static inline ecc_mod_base_t ecc_ll_get_mod_base(void)
 static inline void ecc_ll_enable_constant_time_point_mul(bool enable)
 {
     // ECC constant time point multiplication is supported only on rev 1.2 and above
-    if ((efuse_ll_get_chip_wafer_version_major() >= 1) && (efuse_ll_get_chip_wafer_version_minor() >= 2)) {
+    if (ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102)){
         if (enable) {
             REG_SET_BIT(ECC_MULT_CONF_REG, ECC_MULT_SECURITY_MODE);
         } else {

components/hal/esp32h2/include/hal/ecdsa_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -9,8 +9,10 @@
 #include <string.h>
 #include "hal/assert.h"
 #include "soc/ecdsa_reg.h"
+#include "soc/ecdsa_struct.h"
 #include "soc/pcr_struct.h"
 #include "hal/ecdsa_types.h"
+#include "hal/ecc_ll.h"
 
 #ifdef __cplusplus
 extern "C" {
@@ -31,7 +33,7 @@ typedef enum {
  * @brief Interrupt types in ECDSA
  */
 typedef enum {
-    ECDSA_INT_CALC_DONE,
+    ECDSA_INT_PREP_DONE,
     ECDSA_INT_SHA_RELEASE,
 } ecdsa_ll_intr_type_t;
 
@@ -97,8 +99,8 @@ static inline void ecdsa_ll_reset_register(void)
 static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_CALC_DONE_INT_ENA, 1);
+        case ECDSA_INT_PREP_DONE:
+            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 1);
             break;
         case ECDSA_INT_SHA_RELEASE:
             REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 1);
@@ -117,8 +119,8 @@ static inline void ecdsa_ll_enable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_CALC_DONE_INT_ENA, 0);
+        case ECDSA_INT_PREP_DONE:
+            REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_PREP_DONE_INT_ENA, 0);
             break;
         case ECDSA_INT_SHA_RELEASE:
             REG_SET_FIELD(ECDSA_INT_ENA_REG, ECDSA_SHA_RELEASE_INT_ENA, 0);
@@ -137,8 +139,8 @@ static inline void ecdsa_ll_disable_intr(ecdsa_ll_intr_type_t type)
 static inline void ecdsa_ll_clear_intr(ecdsa_ll_intr_type_t type)
 {
     switch (type) {
-        case ECDSA_INT_CALC_DONE:
-            REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_CALC_DONE_INT_CLR, 1);
+        case ECDSA_INT_PREP_DONE:
+            REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_PREP_DONE_INT_CLR, 1);
             break;
         case ECDSA_INT_SHA_RELEASE:
             REG_SET_FIELD(ECDSA_INT_CLR_REG, ECDSA_SHA_RELEASE_INT_CLR, 1);

components/hal/include/hal/ecdsa_hal.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */

components/hal/test_apps/crypto/main/ecc/test_ecc.c

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: CC0-1.0
  */
@@ -159,12 +159,18 @@ TEST(ecc, ecc_point_multiplication_on_SECP192R1_and_SECP256R1)
     test_ecc_point_mul_inner(false);
 }
 
-#if SOC_ECC_CONSTANT_TIME_POINT_MUL || (CONFIG_IDF_TARGET_ESP32H2 && CONFIG_ESP32H2_REV_MIN_FULL >= 102)
+#if SOC_ECC_CONSTANT_TIME_POINT_MUL
 
 #define CONST_TIME_DEVIATION_PERCENT 0.002
 
 static void test_ecc_point_mul_inner_constant_time(void)
 {
+#if CONFIG_IDF_TARGET_ESP32H2
+    if (!ESP_CHIP_REV_ABOVE(efuse_hal_chip_revision(), 102)) {
+        TEST_IGNORE_MESSAGE("Skipping test, not supported on ESP32-H2 <v1.2\n");
+        return;
+    }
+#endif
     uint8_t scalar_le[32];
     uint8_t x_le[32];
     uint8_t y_le[32];
@@ -559,7 +565,7 @@ TEST_GROUP_RUNNER(ecc)
 {
 #if SOC_ECC_SUPPORT_POINT_MULT
     RUN_TEST_CASE(ecc, ecc_point_multiplication_on_SECP192R1_and_SECP256R1);
-#if SOC_ECC_CONSTANT_TIME_POINT_MUL || (CONFIG_IDF_TARGET_ESP32H2 && CONFIG_ESP32H2_REV_MIN_FULL >= 102)
+#if SOC_ECC_CONSTANT_TIME_POINT_MUL
     RUN_TEST_CASE(ecc, ecc_point_multiplication_const_time_check_on_SECP192R1_and_SECP256R1);
 #endif
 #endif

components/mbedtls/Kconfig

@@ -586,7 +586,7 @@ menu "mbedTLS"
 
     menu "Enable Software Countermeasure for ECDSA signing using on-chip ECDSA peripheral"
         depends on MBEDTLS_HARDWARE_ECDSA_SIGN
-        depends on IDF_TARGET_ESP32H2 && ESP32H2_REV_MIN_FULL < 102
+        depends on IDF_TARGET_ESP32H2
         config MBEDTLS_HARDWARE_ECDSA_SIGN_MASKING_CM
             bool "Mask original ECDSA sign operation under dummy sign operations"
             select HAL_ECDSA_GEN_SIG_CM

components/soc/CMakeLists.txt

@@ -27,6 +27,10 @@ if(target STREQUAL "esp32")
     list(APPEND srcs "${target_folder}/dport_access.c")
 endif()
 
+if(target STREQUAL "esp32h2")
+    list(APPEND srcs "${target_folder}/ecdsa_reg_addr.c")
+endif()
+
 if(CONFIG_SOC_ADC_SUPPORTED)
     list(APPEND srcs "${target_folder}/adc_periph.c")
 endif()

components/soc/esp32h2/ecdsa_reg_addr.c

@@ -0,0 +1,28 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// This file initialises the memory register addresses for the ECDSA accelerator
+// This software initialization is required due to incompatibility between the old and new ECDSA versions
+// for the ESP32-H2 ECDSA accelerator
+#include <stddef.h>
+#include "soc/ecdsa_reg.h"
+
+// Initializing the memory address with the base address of the old ECDSA version
+uint32_t ECDSA_R_MEM = (DR_REG_ECDSA_BASE + 0xA00);
+uint32_t ECDSA_S_MEM = (DR_REG_ECDSA_BASE + 0xA20);
+uint32_t ECDSA_Z_MEM = (DR_REG_ECDSA_BASE + 0xA40);
+uint32_t ECDSA_QAX_MEM = (DR_REG_ECDSA_BASE + 0xA60);
+uint32_t ECDSA_QAY_MEM = (DR_REG_ECDSA_BASE + 0xA80);
+
+void ecdsa_compatible_mem_reg_addr_init(void)
+{
+    // set the memory registers based on the DATE register value
+    ECDSA_R_MEM = (DR_REG_ECDSA_BASE + ECDSA_REG_GET_OFFSET(0xA00, 0x340));
+    ECDSA_S_MEM = (DR_REG_ECDSA_BASE + ECDSA_REG_GET_OFFSET(0xA20, 0x360));
+    ECDSA_Z_MEM = (DR_REG_ECDSA_BASE + ECDSA_REG_GET_OFFSET(0xA40, 0x380));
+    ECDSA_QAX_MEM = (DR_REG_ECDSA_BASE + ECDSA_REG_GET_OFFSET(0xA60, 0x3A0));
+    ECDSA_QAY_MEM = (DR_REG_ECDSA_BASE + ECDSA_REG_GET_OFFSET(0xA80, 0x3C0));
+}

components/soc/esp32h2/include/soc/ecdsa_struct.h

@@ -0,0 +1,53 @@
+/**
+ * SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
+ *
+ *  SPDX-License-Identifier: Apache-2.0
+ */
+#pragma once
+
+#include <stdint.h>
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "soc/ecdsa_rev_0_0_struct.h"
+#include "soc/ecdsa_rev_1_2_struct.h"
+
+/**
+ * @brief Compatible ecdsa struct wrapper
+ *
+ */
+typedef union {
+    volatile ecdsa_dev_rev_0_0_t rev_0_0;
+    volatile ecdsa_dev_rev_1_2_t rev_1_2;
+} ecdsa_dev_t;
+
+extern ecdsa_dev_t ECDSA;
+
+/* Note: For ECDSA register on ESP32-H2, you need to use the ECDSA struct through
+ * ECDSA_REG_GET and ECDSA_REG_SET to access the ECDSA peripheral register and its fields respectively.
+ * For e.g., ECDSA_REG_SET(ECDSA.clk.clk_gate_force_on, enable) is used to set the register value.
+ * The ECDSA struct should not be referenced directly.
+ */
+
+/** The ECDSA date version of chip revision 1.2*/
+#define ECDSA_REV1_2_DATE   (0x2403120)
+
+/**
+ * @brief Set the register value compatibly
+ * @param reg The register to set
+ * @param val The value to set
+ */
+#define ECDSA_REG_SET(reg, val)    (ECDSA.rev_1_2.date.ecdsa_date >= ECDSA_REV1_2_DATE ?  \
+                                     (ECDSA.rev_1_2.reg = (val)) : (ECDSA.rev_0_0.reg = (val)))
+
+/**
+ * @brief Get the register value compatibly
+ * @param reg The register to get
+ */
+#define ECDSA_REG_GET(reg)         (ECDSA.rev_1_2.date.ecdsa_date >= ECDSA_REV1_2_DATE ?  \
+                                     (ECDSA.rev_1_2.reg) : (ECDSA.rev_0_0.reg))
+
+#ifdef __cplusplus
+}
+#endif