Merge branch 'feature/add_120m_clk' into 'master'

feat(clk): Add 120M pll clock support

See merge request espressif/esp-idf!40456

Author: mythbuster5

components/esp_hw_support/port/esp32p4/esp_clk_tree.c

@@ -38,6 +38,9 @@ esp_err_t esp_clk_tree_src_get_freq_hz(soc_module_clk_t clk_src, esp_clk_tree_sr
     case SOC_MOD_CLK_PLL_F80M:
         clk_src_freq = CLK_LL_PLL_80M_FREQ_MHZ * MHZ;
         break;
+    case SOC_MOD_CLK_PLL_F120M:
+        clk_src_freq = CLK_LL_PLL_120M_FREQ_MHZ * MHZ;
+        break;
     case SOC_MOD_CLK_PLL_F160M:
         clk_src_freq = CLK_LL_PLL_160M_FREQ_MHZ * MHZ;
         break;
@@ -126,6 +129,9 @@ esp_err_t esp_clk_tree_enable_src(soc_module_clk_t clk_src, bool enable)
         case SOC_MOD_CLK_PLL_F80M:
             clk_gate_ll_ref_80m_clk_en(enable);
             break;
+        case SOC_MOD_CLK_PLL_F120M:
+            clk_gate_ll_ref_120m_clk_en(enable);
+            break;
         case SOC_MOD_CLK_PLL_F160M:
             clk_gate_ll_ref_160m_clk_en(enable);
             break;

components/hal/esp32p4/include/hal/clk_gate_ll.h

@@ -76,6 +76,21 @@ FORCE_INLINE_ATTR void _clk_gate_ll_ref_160m_clk_en(bool enable)
         _clk_gate_ll_ref_160m_clk_en(__VA_ARGS__); \
     } while(0)
 
+/**
+ * Enable or disable the clock gate for ref_120m.
+ * @param  enable Enable / disable
+ */
+FORCE_INLINE_ATTR void _clk_gate_ll_ref_120m_clk_en(bool enable)
+{
+    HP_SYS_CLKRST.ref_clk_ctrl2.reg_ref_120m_clk_en = enable;
+}
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define clk_gate_ll_ref_120m_clk_en(...) do { \
+        (void)__DECLARE_RCC_ATOMIC_ENV; \
+        _clk_gate_ll_ref_120m_clk_en(__VA_ARGS__); \
+    } while(0)
+
 /**
  * Enable or disable the clock gate for ref_20m.
  * @param  enable Enable / disable

components/hal/esp32p4/include/hal/clk_tree_ll.h

@@ -37,6 +37,7 @@ extern "C" {
 #define CLK_LL_PLL_8M_FREQ_MHZ     (8)
 
 #define CLK_LL_PLL_80M_FREQ_MHZ    (80)
+#define CLK_LL_PLL_120M_FREQ_MHZ   (120)
 #define CLK_LL_PLL_160M_FREQ_MHZ   (160)
 #define CLK_LL_PLL_240M_FREQ_MHZ   (240)
 #define CLK_LL_PLL_SDIO_FREQ_MHZ   (200)

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -163,6 +163,7 @@ typedef enum {
     SOC_MOD_CLK_PLL_F50M,                      /*!< PLL_F50M_CLK is derived from MPLL (clock gating + configurable divider 10), it will have a frequency of 50MHz */
     SOC_MOD_CLK_PLL_F80M,                      /*!< PLL_F80M_CLK is derived from SPLL (clock gating + default divider 6), its default frequency is 80MHz */
     SOC_MOD_CLK_PLL_F160M,                     /*!< PLL_F160M_CLK is derived from SPLL (clock gating + default divider 3), its default frequency is 160MHz */
+    SOC_MOD_CLK_PLL_F120M,                     /*!< PLL_F120M_CLK is derived from SPLL (clock gating + default divider 4), its default frequency is 120MHz */
     SOC_MOD_CLK_PLL_F240M,                     /*!< PLL_F240M_CLK is derived from SPLL (clock gating + default divider 2), its default frequency is 240MHz */
     SOC_MOD_CLK_CPLL,                          /*!< CPLL is from 40MHz XTAL oscillator frequency multipliers */
     SOC_MOD_CLK_SPLL,                          /*!< SPLL is from 40MHz XTAL oscillator frequency multipliers, its default frequency is 480MHz */
@@ -756,6 +757,7 @@ typedef enum {
 typedef enum {
     I3C_MASTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,
     I3C_MASTER_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M,
+    I3C_MASTER_CLK_SRC_PLL_F120M = SOC_MOD_CLK_PLL_F120M,
     I3C_MASTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
 } soc_periph_i3c_master_clk_src_t;