Skip to content

Commit f2742df

Browse files
Icarus113Icarus113
committed
Merge branch 'feat/c61_psram_timing_tuning' into 'master'
psram: psram timing tuning support on c61 Closes IDF-9256 See merge request espressif/esp-idf!40844
2 parents e8ef305 + 0189be3 commit f2742df

File tree

7 files changed

+575
-0
lines changed

7 files changed

+575
-0
lines changed

‎components/esp_hw_support/mspi_timing_tuning/port/esp32c61/CMakeLists.txt‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
target_include_directories(${COMPONENT_LIB} PUBLIC . include)
2+
3+
set(srcs)
4+
5+
if(NOT BOOTLOADER_BUILD)
6+
if(NOT CONFIG_APP_BUILD_TYPE_PURE_RAM_APP)
7+
list(APPEND srcs "mspi_timing_config.c")
8+
endif()
9+
endif()
10+
11+
target_sources(${COMPONENT_LIB} PRIVATE ${srcs})

‎components/esp_hw_support/mspi_timing_tuning/port/esp32c61/mspi_timing_config.c‎

Lines changed: 78 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,78 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
#include <sys/param.h>
8+
#include "sdkconfig.h"
9+
#include "esp_attr.h"
10+
#include "esp_err.h"
11+
#include "esp_types.h"
12+
#include "esp_log.h"
13+
#include "soc/soc_caps.h"
14+
#include "esp_private/periph_ctrl.h"
15+
#include "esp_private/mspi_timing_config.h"
16+
#include "mspi_timing_tuning_configs.h"
17+
#include "hal/psram_ctrlr_ll.h"
18+
#include "hal/mspi_ll.h"
19+
20+
#define FLASH_LOW_SPEED_CORE_CLOCK_MHZ MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT
21+
#define FLASH_HIGH_SPEED_CORE_CLOCK_MHZ MSPI_TIMING_CORE_CLOCK_MHZ
22+
#define PSRAM_LOW_SPEED_CORE_CLOCK_MHZ MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT
23+
#define PSRAM_HIGH_SPEED_CORE_CLOCK_MHZ MSPI_TIMING_CORE_CLOCK_MHZ
24+
25+
const static char *TAG = "MSPI Timing";
26+
27+
//-------------------------------------MSPI Clock Setting-------------------------------------//
28+
static void s_mspi_flash_set_core_clock(uint8_t mspi_id, uint32_t core_clock_mhz)
29+
{
30+
ESP_EARLY_LOGV(TAG, "flash core clock: %d", core_clock_mhz);
31+
mspi_timing_ll_set_core_clock(mspi_id, core_clock_mhz);
32+
}
33+
34+
static void s_mspi_psram_set_core_clock(uint8_t mspi_id, uint32_t core_clock_mhz)
35+
{
36+
ESP_EARLY_LOGV(TAG, "psram core clock: %d", core_clock_mhz);
37+
mspi_timing_ll_set_core_clock(mspi_id, core_clock_mhz);
38+
}
39+
40+
void mspi_timing_config_set_flash_clock(uint32_t flash_freq_mhz, mspi_timing_speed_mode_t speed_mode, bool control_both_mspi)
41+
{
42+
uint32_t core_clock_mhz = 0;
43+
if (speed_mode == MSPI_TIMING_SPEED_MODE_LOW_PERF) {
44+
core_clock_mhz = FLASH_LOW_SPEED_CORE_CLOCK_MHZ;
45+
} else {
46+
core_clock_mhz = FLASH_HIGH_SPEED_CORE_CLOCK_MHZ;
47+
}
48+
//SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
49+
s_mspi_flash_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, core_clock_mhz);
50+
51+
uint32_t freqdiv = core_clock_mhz / flash_freq_mhz;
52+
ESP_EARLY_LOGV(TAG, "flash freqdiv: %d", freqdiv);
53+
assert(freqdiv > 0);
54+
uint32_t reg_val = mspi_timing_ll_calculate_clock_reg(freqdiv);
55+
mspi_timing_ll_set_flash_clock(MSPI_TIMING_LL_MSPI_ID_0, reg_val);
56+
if (control_both_mspi) {
57+
mspi_timing_ll_set_flash_clock(MSPI_TIMING_LL_MSPI_ID_1, reg_val);
58+
}
59+
}
60+
61+
void mspi_timing_config_set_psram_clock(uint32_t psram_freq_mhz, mspi_timing_speed_mode_t speed_mode, bool control_both_mspi)
62+
{
63+
(void)control_both_mspi; // for compatibility
64+
uint32_t core_clock_mhz = 0;
65+
if (speed_mode == MSPI_TIMING_SPEED_MODE_LOW_PERF) {
66+
core_clock_mhz = PSRAM_LOW_SPEED_CORE_CLOCK_MHZ;
67+
} else {
68+
core_clock_mhz = PSRAM_HIGH_SPEED_CORE_CLOCK_MHZ;
69+
}
70+
//SPI0 and SPI1 share the register for core clock. So we only set SPI0 here.
71+
s_mspi_psram_set_core_clock(MSPI_TIMING_LL_MSPI_ID_0, core_clock_mhz);
72+
73+
uint32_t freqdiv = core_clock_mhz / psram_freq_mhz;
74+
ESP_EARLY_LOGV(TAG, "psram freqdiv: %d", freqdiv);
75+
assert(freqdiv > 0);
76+
uint32_t reg_val = mspi_timing_ll_calculate_clock_reg(freqdiv);
77+
mspi_timing_ll_set_psram_clock(MSPI_TIMING_LL_MSPI_ID_0, reg_val);
78+
}

‎components/esp_hw_support/mspi_timing_tuning/port/esp32c61/mspi_timing_tuning_configs.h‎

Lines changed: 119 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,119 @@
1+
/*
2+
* SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
#pragma once
7+
8+
#include "sdkconfig.h"
9+
#include "esp_assert.h"
10+
#include "esp_flash_partitions.h"
11+
12+
#define MSPI_TIMING_MSPI1_IS_INVOLVED CONFIG_ESPTOOLPY_FLASHFREQ_120M //This means esp flash driver needs to be notified
13+
#define MSPI_TIMING_CONFIG_NUM_MAX 32 //This should be larger than the max available timing config num
14+
#define MSPI_TIMING_TEST_DATA_LEN 128
15+
#define MSPI_TIMING_PSRAM_TEST_DATA_ADDR 0x100000
16+
17+
//--------------------------------------FLASH Sampling Mode --------------------------------------//
18+
#define MSPI_TIMING_FLASH_STR_MODE 1
19+
//--------------------------------------FLASH Module Clock --------------------------------------//
20+
#if CONFIG_ESPTOOLPY_FLASHFREQ_20M
21+
#define MSPI_TIMING_FLASH_MODULE_CLOCK 20
22+
#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
23+
#define MSPI_TIMING_FLASH_MODULE_CLOCK 40
24+
#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M
25+
#define MSPI_TIMING_FLASH_MODULE_CLOCK 80
26+
#elif CONFIG_ESPTOOLPY_FLASHFREQ_120M
27+
#define MSPI_TIMING_FLASH_MODULE_CLOCK 120
28+
#endif
29+
//------------------------------------FLASH Needs Tuning or not-------------------------------------//
30+
#define MSPI_TIMING_FLASH_NEEDS_TUNING 0
31+
32+
//--------------------------------------PSRAM Sampling Mode --------------------------------------//
33+
#define MSPI_TIMING_PSRAM_STR_MODE 1
34+
//--------------------------------------PSRAM Module Clock --------------------------------------//
35+
#if CONFIG_SPIRAM
36+
#if CONFIG_SPIRAM_SPEED_40M
37+
#define MSPI_TIMING_PSRAM_MODULE_CLOCK 40
38+
#elif CONFIG_SPIRAM_SPEED_80M
39+
#define MSPI_TIMING_PSRAM_MODULE_CLOCK 80
40+
#endif
41+
#else //Disable PSRAM
42+
#define MSPI_TIMING_PSRAM_MODULE_CLOCK 10 //Define this to 10MHz
43+
#endif
44+
//------------------------------------PSRAM Needs Tuning or not-------------------------------------//
45+
#if MSPI_TIMING_PSRAM_STR_MODE
46+
#define MSPI_TIMING_PSRAM_NEEDS_TUNING (MSPI_TIMING_PSRAM_MODULE_CLOCK > 40)
47+
#endif
48+
49+
///////////////////////////////////// FLASH/PSRAM CORE CLOCK /////////////////////////////////////
50+
#if ((CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_SPIRAM) || (CONFIG_ESPTOOLPY_FLASHFREQ_80M && CONFIG_SPIRAM_SPEED_80M))
51+
#define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 80
52+
#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 80
53+
#define MSPI_TIMING_FLASH_CONSECUTIVE_LEN_MAX 6
54+
#else
55+
#define MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ 240
56+
#define MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ 240
57+
#define MSPI_TIMING_FLASH_CONSECUTIVE_LEN_MAX 4
58+
#endif
59+
60+
//------------------------------------------Determine the Core Clock-----------------------------------------------//
61+
/**
62+
* @note
63+
* Limitation 1:
64+
* MSPI FLASH and PSRAM share the core clock register. Therefore,
65+
* the expected CORE CLOCK frequencies should be the same.
66+
*/
67+
#if MSPI_TIMING_FLASH_NEEDS_TUNING && MSPI_TIMING_PSRAM_NEEDS_TUNING
68+
ESP_STATIC_ASSERT(MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ == MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ, "FLASH and PSRAM Mode configuration are not supported");
69+
#define MSPI_TIMING_CORE_CLOCK_MHZ MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
70+
71+
//If only FLASH needs tuning, the core clock COULD be as FLASH expected
72+
#elif MSPI_TIMING_FLASH_NEEDS_TUNING && !MSPI_TIMING_PSRAM_NEEDS_TUNING
73+
ESP_STATIC_ASSERT(MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_PSRAM_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported");
74+
#define MSPI_TIMING_CORE_CLOCK_MHZ MSPI_TIMING_FLASH_EXPECTED_CORE_CLK_MHZ
75+
76+
//If only PSRAM needs tuning, the core clock COULD be as PSRAM expected
77+
#elif !MSPI_TIMING_FLASH_NEEDS_TUNING && MSPI_TIMING_PSRAM_NEEDS_TUNING
78+
ESP_STATIC_ASSERT(MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ % MSPI_TIMING_FLASH_MODULE_CLOCK == 0, "FLASH and PSRAM Mode configuration are not supported");
79+
#define MSPI_TIMING_CORE_CLOCK_MHZ MSPI_TIMING_PSRAM_EXPECTED_CORE_CLK_MHZ
80+
81+
#else
82+
#define MSPI_TIMING_CORE_CLOCK_MHZ 80
83+
#endif
84+
85+
86+
//------------------------------------------Helper Macros to get FLASH/PSRAM tuning configs-----------------------------------------------//
87+
#define __GET_TUNING_CONFIG(type, core_clock, module_clock, mode) \
88+
(mspi_timing_config_t) { .tuning_config_table = MSPI_TIMING_##type##_CONFIG_TABLE_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \
89+
.available_config_num = MSPI_TIMING_##type##_CONFIG_NUM_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode, \
90+
.default_config_id = MSPI_TIMING_##type##_DEFAULT_CONFIG_ID_CORE_CLK_##core_clock##M_MODULE_CLK_##module_clock##M_##mode }
91+
92+
#define _GET_TUNING_CONFIG(type, core_clock, module_clock, mode) __GET_TUNING_CONFIG(type, core_clock, module_clock, mode)
93+
94+
#define MSPI_TIMING_FLASH_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(FLASH, core_clock_mhz, module_clock_mhz, mode)
95+
#define MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(core_clock_mhz, module_clock_mhz, mode) _GET_TUNING_CONFIG(PSRAM, core_clock_mhz, module_clock_mhz, mode)
96+
97+
98+
/**
99+
* Timing Tuning Parameters
100+
*/
101+
//FLASH: core clock 80M, module clock 80M, STR mode
102+
#define MSPI_TIMING_FLASH_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}}
103+
#define MSPI_TIMING_FLASH_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 14
104+
#define MSPI_TIMING_FLASH_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 4
105+
106+
//PSRAM: core clock 240M, module clock 120M, STR mode
107+
#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE {{2, 0, 1}, {0, 0, 0}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {2, 2, 3}, {2, 1, 3}, {2, 0, 3}, {0, 0, 2}, {2, 2, 4}, {2, 1, 4}}
108+
#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 12
109+
#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_120M_STR_MODE 4
110+
111+
//PSRAM: core clock 240M, module clock 80M, STR mode
112+
#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}}
113+
#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE 14
114+
#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_240M_MODULE_CLK_80M_STR_MODE 4
115+
116+
//PSRAM: core clock 80M, module clock 80M, STR mode
117+
#define MSPI_TIMING_PSRAM_CONFIG_TABLE_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE {{2, 2, 1}, {2, 1, 1}, {2, 0, 1}, {0, 0, 0}, {3, 1, 2}, {2, 3, 2}, {2, 2, 2}, {2, 1, 2}, {2, 0, 2}, {0, 0, 1}, {3, 1, 3}, {2, 3, 3}, {2, 2, 3}, {2, 1, 3}}
118+
#define MSPI_TIMING_PSRAM_CONFIG_NUM_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 14
119+
#define MSPI_TIMING_PSRAM_DEFAULT_CONFIG_ID_CORE_CLK_80M_MODULE_CLK_80M_STR_MODE 4

0 commit comments

Comments
 (0)