Merge branch 'reproduce/32_spi_slave_hold_miso_when_deactive' into 'master'

fix(driver_spi): add some parameter checks

Closes IDFGH-7020, IDFGH-262, and IDFGH-16313

See merge request espressif/esp-idf!21648

Author: suda-morris

components/esp_driver_spi/src/gpspi/spi_master.c

@@ -665,10 +665,10 @@ static SPI_MASTER_ISR_ATTR void spi_setup_device(spi_device_t *dev, spi_trans_pr
             .use_gpio = !(dev->host->bus_attr->flags & SPICOMMON_BUSFLAG_IOMUX_PINS),
         };
 
-        if (ESP_OK == spi_hal_cal_clock_conf(&timing_param, &dev->hal_dev.timing_conf)) {
+        if ((trans_buf->trans->override_freq_hz <= SPI_PERIPH_SRC_FREQ_MAX) && (ESP_OK == spi_hal_cal_clock_conf(&timing_param, &dev->hal_dev.timing_conf))) {
             clock_changed = true;
         } else {
-            ESP_EARLY_LOGW(SPI_TAG, "assigned clock speed %d not supported", trans_buf->trans->override_freq_hz);
+            ESP_EARLY_LOGW(SPI_TAG, "assigned override_freq_hz %d not supported", trans_buf->trans->override_freq_hz);
         }
     }
 

components/esp_driver_spi/src/gpspi/spi_slave.c

@@ -407,9 +407,13 @@ esp_err_t spi_slave_disable(spi_host_device_t host)
 
 static void SPI_SLAVE_ISR_ATTR spi_slave_uninstall_priv_trans(spi_host_device_t host, spi_slave_trans_priv_t *priv_trans)
 {
+    __attribute__((unused)) spi_slave_transaction_t *trans = (spi_slave_transaction_t *)priv_trans->trans;
+#if CONFIG_IDF_TARGET_ESP32
+    if (spihost[host]->dma_enabled && (trans->trans_len % 32)) {
+        ESP_EARLY_LOGW(SPI_TAG, "Use DMA but real trans_len is not 4 bytes aligned, slave may loss data");
+    }
+#endif
 #if SOC_CACHE_INTERNAL_MEM_VIA_L1CACHE
-    spi_slave_transaction_t *trans = (spi_slave_transaction_t *)priv_trans->trans;
-
     if (spihost[host]->dma_enabled) {
         if (trans->tx_buffer && (trans->tx_buffer != priv_trans->tx_buffer)) {
             free(priv_trans->tx_buffer);

docs/en/api-reference/peripherals/spi_slave.rst

@@ -258,6 +258,10 @@ Restrictions and Known Issues
 
     If DMA is enabled, a Device's launch edge is half of an SPI clock cycle ahead of the normal time, shifting to the Master's actual latch edge. In this case, if the GPIO matrix is bypassed, the hold time for data sampling is 68.75 ns and no longer a half of an SPI clock cycle. If the GPIO matrix is used, the hold time will increase to 93.75 ns. The Host should sample the data immediately at the latch edge or communicate in SPI modes 1 or 3. If your Host cannot meet these timing requirements, initialize your Device without DMA.
 
+    3. ESP32 SPI Slave **still** outputs the level 0/1 on the MISO pin even when the CS line is not asserted, which may cause other devices on the bus to output incorrect data. The solution is:
+
+      1) Use a separate bus for the ESP32 SPI Slave, not sharing it with other devices.
+      2) Add a buffer chip between the ESP32 SPI MISO pin and the bus, such as 74HC125.
 
 Application Examples
 --------------------

docs/zh_CN/api-reference/peripherals/spi_slave.rst

@@ -258,6 +258,10 @@ SPI 从机的工作频率最高可达 {IDF_TARGET_MAX_FREQ} MHz。如果时钟
 
     如果启用 DMA，从机设备的发射沿会比正常时间提前半个 SPI 时钟周期，变为主机的实际锁存沿。在这种情况下，如果 GPIO 交换矩阵被绕过，数据采样的保持时间将是 68.75 ns，而非半个 SPI 时钟周期。如果使用了 GPIO 交换矩阵，保持时间将增加到 93.75 ns。主机应在锁存沿立即采样数据，或在 SPI 模式 1 或模式 3 中进行通信。如果主机无法满足上述时间要求，请在没有 DMA 的情况下初始化从机设备。
 
+    3. ESP32 SPI Slave 在 CS 片选未使能时 **仍然** 在 MISO 引脚输出电平 0/1, 这可能导致总线上其他设备无法正确输出数据，解决方法为：
+
+      1) 为 ESP32 SPI Slave 单独使用一条总线，不与其他设备共享总线。
+      2) 在 ESP32 SPI MISO 引脚和总线之间增加缓冲器芯片，如 74HC125。
 
 应用示例
 -------------------