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Meet Patel
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refactor(ulp_riscv): Modify ulp i2c read/write functions to return error code
Updated the i2c read/write APIs ulp_riscv_i2c_master_read_from_device and ulp_riscv_i2c_master_write_to_device in ulp_riscv component to return error codes back to the application Closes #15904
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4 files changed

+35
-15
lines changed

4 files changed

+35
-15
lines changed

‎components/ulp/ulp_riscv/include/ulp_riscv_i2c.h‎

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -114,8 +114,9 @@ void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr);
114114
*
115115
* @param data_rd Buffer to hold data to be read
116116
* @param size Size of data to be read in bytes
117+
* @return esp_err_t ESP_OK when successful
117118
*/
118-
void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
119+
esp_err_t ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
119120

120121
/**
121122
* @brief Write to I2C slave device
@@ -124,8 +125,9 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
124125
*
125126
* @param data_wr Buffer which holds the data to be written
126127
* @param size Size of data to be written in bytes
128+
* @return esp_err_t ESP_OK when successful
127129
*/
128-
void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size);
130+
esp_err_t ulp_riscv_i2c_master_write_to_device(const uint8_t *data_wr, size_t size);
129131

130132
/**
131133
* @brief Initialize and configure the RTC I2C for use by ULP RISC-V

‎components/ulp/ulp_riscv/ulp_core/include/ulp_riscv_i2c_ulp_core.h‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
@@ -12,6 +12,7 @@ extern "C" {
1212

1313
#include <stddef.h>
1414
#include <stdint.h>
15+
#include "esp_err.h"
1516

1617
/**
1718
* @brief Set the I2C slave device address
@@ -34,8 +35,9 @@ void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr);
3435
*
3536
* @param data_rd Buffer to hold data to be read
3637
* @param size Size of data to be read in bytes
38+
* @return esp_err_t ESP_OK when successful
3739
*/
38-
void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
40+
esp_err_t ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
3941

4042
/**
4143
* @brief Write to I2C slave device
@@ -44,8 +46,9 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size);
4446
*
4547
* @param data_wr Buffer which holds the data to be written
4648
* @param size Size of data to be written in bytes
49+
* @return esp_err_t ESP_OK when successful
4750
*/
48-
void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size);
51+
esp_err_t ulp_riscv_i2c_master_write_to_device(const uint8_t *data_wr, size_t size);
4952

5053
#ifdef __cplusplus
5154
}

‎components/ulp/ulp_riscv/ulp_core/ulp_riscv_i2c.c‎

Lines changed: 14 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,9 @@
11
/*
2-
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
2+
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
33
*
44
* SPDX-License-Identifier: Apache-2.0
55
*/
6+
#include "esp_err.h"
67
#include "ulp_riscv_i2c_ulp_core.h"
78
#include "ulp_riscv_utils.h"
89
#include "soc/rtc_i2c_reg.h"
@@ -131,14 +132,15 @@ void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr)
131132
* | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | |
132133
* |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|--------|--------|
133134
*/
134-
void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
135+
esp_err_t ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
135136
{
136137
uint32_t i = 0;
137138
uint32_t cmd_idx = 0;
139+
esp_err_t ret = ESP_OK;
138140

139141
if (size == 0) {
140142
// Quietly return
141-
return;
143+
return ESP_ERR_INVALID_ARG;
142144
}
143145

144146
// Workaround for IDF-9145
@@ -197,6 +199,7 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
197199
} else {
198200
/* Error in transaction */
199201
CLEAR_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, READ_PERI_REG(RTC_I2C_INT_ST_REG));
202+
ret = ESP_ERR_INVALID_RESPONSE;
200203
break;
201204
}
202205
}
@@ -207,6 +210,8 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
207210

208211
// Workaround for IDF-9145
209212
ULP_RISCV_EXIT_CRITICAL();
213+
214+
return ret;
210215
}
211216

212217
/*
@@ -226,14 +231,15 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
226231
* | Slave | | | ACK | | ACK | | ACK | | ACK | |
227232
* |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------|
228233
*/
229-
void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
234+
esp_err_t ulp_riscv_i2c_master_write_to_device(const uint8_t *data_wr, size_t size)
230235
{
231236
uint32_t i = 0;
232237
uint32_t cmd_idx = 0;
238+
esp_err_t ret = ESP_OK;
233239

234240
if (size == 0) {
235241
// Quietly return
236-
return;
242+
return ESP_ERR_INVALID_ARG;
237243
}
238244

239245
// Workaround for IDF-9145
@@ -271,6 +277,7 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
271277
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, RTC_I2C_TX_DATA_INT_CLR);
272278
} else {
273279
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, READ_PERI_REG(RTC_I2C_INT_ST_REG));
280+
ret = ESP_ERR_INVALID_RESPONSE;
274281
break;
275282
}
276283
}
@@ -281,4 +288,6 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
281288

282289
// Workaround for IDF-9145
283290
ULP_RISCV_EXIT_CRITICAL();
291+
292+
return ret;
284293
}

‎components/ulp/ulp_riscv/ulp_riscv_i2c.c‎

Lines changed: 10 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -316,7 +316,7 @@ void ulp_riscv_i2c_master_set_slave_reg_addr(uint8_t slave_reg_addr)
316316
* | Slave | | | ACK | | ACK | | | ACK | DATA | | DATA | | |
317317
* |--------|--------|---------|--------|--------|--------|--------|---------|--------|--------|--------|--------|--------|--------|
318318
*/
319-
void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
319+
esp_err_t ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
320320
{
321321
uint32_t i = 0;
322322
uint32_t cmd_idx = 0;
@@ -325,7 +325,7 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
325325

326326
if (size == 0) {
327327
// Quietly return
328-
return;
328+
return ESP_ERR_INVALID_ARG;
329329
}
330330

331331
/* By default, RTC I2C controller is hard wired to use CMD2 register onwards for read operations */
@@ -382,6 +382,7 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
382382
} else {
383383
status = READ_PERI_REG(RTC_I2C_INT_RAW_REG);
384384
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status);
385+
ret = ESP_ERR_INVALID_RESPONSE;
385386
break;
386387
}
387388
}
@@ -397,6 +398,8 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
397398
/* Clear the RTC I2C transmission bits */
398399
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE);
399400
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START);
401+
402+
return ret;
400403
}
401404

402405
/*
@@ -416,7 +419,7 @@ void ulp_riscv_i2c_master_read_from_device(uint8_t *data_rd, size_t size)
416419
* | Slave | | | ACK | | ACK | | ACK | | ACK | |
417420
* |--------|--------|---------|--------|--------|--------|--------|--------|--------|--------|--------|
418421
*/
419-
void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
422+
esp_err_t ulp_riscv_i2c_master_write_to_device(const uint8_t *data_wr, size_t size)
420423
{
421424
uint32_t i = 0;
422425
uint32_t cmd_idx = 0;
@@ -425,7 +428,7 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
425428

426429
if (size == 0) {
427430
// Quietly return
428-
return;
431+
return ESP_ERR_INVALID_ARG;
429432
}
430433

431434
/* By default, RTC I2C controller is hard wired to use CMD0 and CMD1 registers for write operations */
@@ -462,6 +465,7 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
462465
} else {
463466
status = READ_PERI_REG(RTC_I2C_INT_RAW_REG);
464467
SET_PERI_REG_MASK(RTC_I2C_INT_CLR_REG, status);
468+
ret = ESP_ERR_INVALID_RESPONSE;
465469
break;
466470
}
467471
}
@@ -478,6 +482,8 @@ void ulp_riscv_i2c_master_write_to_device(uint8_t *data_wr, size_t size)
478482
/* Clear the RTC I2C transmission bits */
479483
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START_FORCE);
480484
CLEAR_PERI_REG_MASK(SENS_SAR_I2C_CTRL_REG, SENS_SAR_I2C_START);
485+
486+
return ret;
481487
}
482488

483489
esp_err_t ulp_riscv_i2c_master_init(const ulp_riscv_i2c_cfg_t *cfg)

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