2929#include "pwm_audio.h"
3030#include "sdkconfig.h"
3131
32- #if (CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 )
32+ #if (CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S3 )
3333
3434static const char * TAG = "pwm_audio" ;
3535
@@ -121,7 +121,7 @@ static esp_err_t rb_destroy(ringbuf_handle_t *rb)
121121 rb = NULL ;
122122 return ESP_OK ;
123123}
124- static ringbuf_handle_t * rb_create (uint32_t size )
124+ static ringbuf_handle_t * rb_create (uint32_t size )
125125{
126126 if (size < (BUFFER_MIN_SIZE << 2 )) {
127127 ESP_LOGE (TAG , "Invalid buffer size, Minimum = %d" , (int32_t )(BUFFER_MIN_SIZE << 2 ));
@@ -260,31 +260,13 @@ static void IRAM_ATTR timer_group_isr(void *para)
260260 if (handle == NULL ) {
261261 return ;
262262 }
263-
264- #ifdef CONFIG_IDF_TARGET_ESP32S2
265-
266263 /* Clear the interrupt */
267- if (( handle -> timg_dev ) -> int_st . val & BIT (handle -> config .timer_num )) {
268- ( handle -> timg_dev ) -> int_clr . val |= ( 1UL << handle -> config .timer_num );
264+ if (REG_GET_BIT ( TIMG_INT_ST_TIMERS_REG ( handle -> config . timer_num ), BIT (handle -> config .timer_num ) )) {
265+ REG_SET_BIT ( TIMG_INT_CLR_TIMERS_REG ( handle -> config . timer_num ), BIT ( handle -> config .timer_num ) );
269266 }
270-
271267 /* After the alarm has been triggered
272- we need enable it again, so it is triggered the next time */
273- handle -> timg_dev -> hw_timer [handle -> config .timer_num ].config .alarm_en = TIMER_ALARM_EN ;
274- #endif /**< CONFIG_IDF_TARGET_ESP32S2 */
275-
276- #ifdef CONFIG_IDF_TARGET_ESP32
277-
278- /* Clear the interrupt */
279- if (handle -> timg_dev -> int_st_timers .val & BIT (handle -> config .timer_num )) {
280- handle -> timg_dev -> int_clr_timers .val |= (1UL << handle -> config .timer_num );
281- }
282-
283- /* After the alarm has been triggered
284- we need enable it again, so it is triggered the next time */
285- handle -> timg_dev -> hw_timer [handle -> config .timer_num ].config .alarm_en = TIMER_ALARM_EN ;
286-
287- #endif /**< CONFIG_IDF_TARGET_ESP32 */
268+ we need enable it again, so it is triggered the next time */
269+ REG_SET_BIT (TIMG_T0CONFIG_REG (handle -> config .timer_num ), TIMG_T0_ALARM_EN_M );
288270
289271 static uint8_t wave_h , wave_l ;
290272 static uint16_t value ;
@@ -557,7 +539,7 @@ esp_err_t pwm_audio_set_param(int rate, ledc_timer_bit_t bits, int ch)
557539 timer_set_counter_value (handle -> config .tg_num , handle -> config .timer_num , 0x00000000ULL );
558540
559541 /* Configure the alarm value and the interrupt on alarm. */
560- uint32_t divider = handle -> timg_dev -> hw_timer [ handle -> config .timer_num ]. config . divider ;
542+ uint32_t divider = REG_GET_FIELD ( TIMG_T0CONFIG_REG ( handle -> config .timer_num ), TIMG_T0_DIVIDER ) ;
561543 timer_set_alarm_value (handle -> config .tg_num , handle -> config .timer_num , (TIMER_BASE_CLK / divider ) / handle -> framerate );
562544 // timer_enable_intr(handle->config.tg_num, handle->config.timer_num);
563545 return res ;
@@ -572,7 +554,7 @@ esp_err_t pwm_audio_set_sample_rate(int rate)
572554
573555 pwm_audio_data_t * handle = g_pwm_audio_handle ;
574556 handle -> framerate = rate ;
575- uint32_t divider = handle -> timg_dev -> hw_timer [ handle -> config .timer_num ]. config . divider ;
557+ uint32_t divider = REG_GET_FIELD ( TIMG_T0CONFIG_REG ( handle -> config .timer_num ), TIMG_T0_DIVIDER ) ;
576558 res = timer_set_alarm_value (handle -> config .tg_num , handle -> config .timer_num , (TIMER_BASE_CLK / divider ) / handle -> framerate );
577559 return res ;
578560}
@@ -751,10 +733,12 @@ esp_err_t pwm_audio_start(void)
751733
752734 /**< timer enable interrupt */
753735 portENTER_CRITICAL_SAFE (& timer_spinlock );
754- handle -> timg_dev -> int_ena .val |= BIT (handle -> config .timer_num );
755- handle -> timg_dev -> hw_timer [handle -> config .timer_num ].config .enable = 1 ;
756- handle -> timg_dev -> hw_timer [handle -> config .timer_num ].config .alarm_en = TIMER_ALARM_EN ; /** Make sure the interrupt is enabled*/
757- handle -> timg_dev -> hw_timer [handle -> config .timer_num ].config .level_int_en = 1 ;
736+ REG_SET_BIT (TIMG_INT_ENA_TIMERS_REG (handle -> config .timer_num ), BIT (handle -> config .timer_num ));
737+ REG_SET_BIT (TIMG_T0CONFIG_REG (handle -> config .timer_num ), TIMG_T0_EN_M );
738+ REG_SET_BIT (TIMG_T0CONFIG_REG (handle -> config .timer_num ), TIMG_T0_ALARM_EN_M );
739+ #ifdef TIMG_T0_LEVEL_INT_EN_M
740+ REG_SET_BIT (TIMG_T0CONFIG_REG (handle -> config .timer_num ), TIMG_T0_LEVEL_INT_EN_M );
741+ #endif
758742 portEXIT_CRITICAL_SAFE (& timer_spinlock );
759743
760744 res = timer_start (handle -> config .tg_num , handle -> config .timer_num );
@@ -770,9 +754,12 @@ esp_err_t pwm_audio_stop(void)
770754 /**< just disable timer ,keep pwm output to reduce switching nosie */
771755 /**< timer disable interrupt */
772756 portENTER_CRITICAL_SAFE (& timer_spinlock );
773- handle -> timg_dev -> hw_timer [handle -> config .timer_num ].config .enable = 0 ;
774- handle -> timg_dev -> int_ena .val &= (~BIT (handle -> config .timer_num ));
775- handle -> timg_dev -> hw_timer [handle -> config .timer_num ].config .level_int_en = 0 ;
757+ REG_CLR_BIT (TIMG_INT_ENA_TIMERS_REG (handle -> config .timer_num ), BIT (handle -> config .timer_num ));
758+ REG_CLR_BIT (TIMG_T0CONFIG_REG (handle -> config .timer_num ), TIMG_T0_EN_M );
759+ REG_CLR_BIT (TIMG_T0CONFIG_REG (handle -> config .timer_num ), TIMG_T0_ALARM_EN_M );
760+ #ifdef TIMG_T0_LEVEL_INT_EN_M
761+ REG_CLR_BIT (TIMG_T0CONFIG_REG (handle -> config .timer_num ), TIMG_T0_LEVEL_INT_EN_M );
762+ #endif
776763 portEXIT_CRITICAL_SAFE (& timer_spinlock );
777764
778765 // timer_pause(handle->config.tg_num, handle->config.timer_num);
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