feat: add soc header for targets

Author: antmak

src/target/esp32/include/soc/soc.h

@@ -0,0 +1,57 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+/* Overall memory map */
+#define SOC_DROM_LOW 0x3F400000
+#define SOC_DROM_HIGH 0x3F800000
+#define SOC_DRAM_LOW 0x3FFAE000
+#define SOC_DRAM_HIGH 0x40000000
+#define SOC_IROM_LOW 0x400D0000
+#define SOC_IROM_HIGH 0x40400000
+#define SOC_IROM_MASK_LOW 0x40000000
+#define SOC_IROM_MASK_HIGH 0x40070000
+#define SOC_CACHE_PRO_LOW 0x40070000
+#define SOC_CACHE_PRO_HIGH 0x40078000
+#define SOC_CACHE_APP_LOW 0x40078000
+#define SOC_CACHE_APP_HIGH 0x40080000
+#define SOC_IRAM_LOW 0x40080000
+#define SOC_IRAM_HIGH 0x400AA000
+#define SOC_RTC_IRAM_LOW 0x400C0000
+#define SOC_RTC_IRAM_HIGH 0x400C2000
+#define SOC_RTC_DRAM_LOW 0x3FF80000
+#define SOC_RTC_DRAM_HIGH 0x3FF82000
+#define SOC_RTC_DATA_LOW 0x50000000
+#define SOC_RTC_DATA_HIGH 0x50002000
+#define SOC_EXTRAM_DATA_LOW 0x3F800000
+#define SOC_EXTRAM_DATA_HIGH 0x3FC00000
+
+#define SOC_EXTRAM_DATA_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW)
+
+//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
+#define SOC_DIRAM_IRAM_LOW 0x400A0000
+#define SOC_DIRAM_IRAM_HIGH 0x400C0000
+#define SOC_DIRAM_DRAM_LOW 0x3FFE0000
+#define SOC_DIRAM_DRAM_HIGH 0x40000000
+// Byte order of D/IRAM regions is reversed between accessing as DRAM or IRAM
+#define SOC_DIRAM_INVERTED 1
+
+// Region of memory accessible via DMA. See esp_ptr_dma_capable().
+#define SOC_DMA_LOW 0x3FFAE000
+#define SOC_DMA_HIGH 0x40000000
+
+// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
+#define SOC_BYTE_ACCESSIBLE_LOW 0x3FF90000
+#define SOC_BYTE_ACCESSIBLE_HIGH 0x40000000
+
+//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
+//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
+#define SOC_MEM_INTERNAL_LOW 0x3FF90000
+#define SOC_MEM_INTERNAL_HIGH 0x400C2000
+
+// Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START 0x3ffe3f20

src/target/esp32/include/soc/soc_caps.h

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+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+/* Capabilities */
+
+#define SOC_RTC_FAST_MEM_SUPPORTED 1
+#define SOC_RTC_SLOW_MEM_SUPPORTED 1
+#define SOC_RTC_MEM_SUPPORTED 1

src/target/esp32c2/include/soc/soc.h

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+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+/* Overall memory map */
+#define SOC_DROM_LOW 0x3C000000
+#define SOC_DROM_HIGH 0x3C400000
+#define SOC_IROM_LOW 0x42000000
+#define SOC_IROM_HIGH 0x42400000
+#define SOC_IROM_MASK_LOW 0x40000000
+#define SOC_IROM_MASK_HIGH 0x40090000
+#define SOC_DROM_MASK_LOW 0x3FF00000
+#define SOC_DROM_MASK_HIGH 0x3FF50000
+#define SOC_IRAM_LOW 0x4037C000
+#define SOC_IRAM_HIGH 0x403C0000
+#define SOC_DRAM_LOW 0x3FCA0000
+#define SOC_DRAM_HIGH 0x3FCE0000
+
+//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
+#define SOC_DIRAM_IRAM_LOW 0x40380000
+#define SOC_DIRAM_IRAM_HIGH 0x403C0000
+#define SOC_DIRAM_DRAM_LOW 0x3FCA0000
+#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000
+
+#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
+#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
+#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
+
+// Region of memory accessible via DMA. See esp_ptr_dma_capable().
+#define SOC_DMA_LOW 0x3FCA0000
+#define SOC_DMA_HIGH 0x3FCE0000
+
+// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
+#define SOC_BYTE_ACCESSIBLE_LOW 0x3FCA0000
+#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FCE0000
+
+//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
+//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
+#define SOC_MEM_INTERNAL_LOW 0x3FCA0000
+#define SOC_MEM_INTERNAL_HIGH 0x3FCE0000
+
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+
+// Region of address space that holds peripherals
+#define SOC_PERIPHERAL_LOW 0x60000000
+#define SOC_PERIPHERAL_HIGH 0x60100000
+
+// Debug region, not used by software
+#define SOC_DEBUG_LOW 0x20000000
+#define SOC_DEBUG_HIGH 0x28000000
+
+// Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START 0x3fcdeb70
+#define SOC_ROM_STACK_SIZE 0x2000

src/target/esp32c2/include/soc/soc_caps.h

@@ -0,0 +1,9 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+/* Capabilities */

src/target/esp32c3/include/soc/soc.h

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+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+/* Overall memory map */
+#define SOC_DROM_LOW 0x3C000000
+#define SOC_DROM_HIGH 0x3C800000
+#define SOC_IROM_LOW 0x42000000
+#define SOC_IROM_HIGH 0x42800000
+#define SOC_IROM_MASK_LOW 0x40000000
+#define SOC_IROM_MASK_HIGH 0x40060000
+#define SOC_DROM_MASK_LOW 0x3FF00000
+#define SOC_DROM_MASK_HIGH 0x3FF20000
+#define SOC_IRAM_LOW 0x4037C000
+#define SOC_IRAM_HIGH 0x403E0000
+#define SOC_DRAM_LOW 0x3FC80000
+#define SOC_DRAM_HIGH 0x3FCE0000
+#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C3 only has RTC slow memory
+#define SOC_RTC_IRAM_HIGH 0x50002000
+#define SOC_RTC_DRAM_LOW 0x50000000
+#define SOC_RTC_DRAM_HIGH 0x50002000
+#define SOC_RTC_DATA_LOW 0x50000000
+#define SOC_RTC_DATA_HIGH 0x50002000
+
+//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
+#define SOC_DIRAM_IRAM_LOW 0x40380000
+#define SOC_DIRAM_IRAM_HIGH 0x403E0000
+#define SOC_DIRAM_DRAM_LOW 0x3FC80000
+#define SOC_DIRAM_DRAM_HIGH 0x3FCE0000
+
+#define SOC_I_D_OFFSET (SOC_DIRAM_IRAM_LOW - SOC_DIRAM_DRAM_LOW)
+#define MAP_DRAM_TO_IRAM(addr) (addr + SOC_I_D_OFFSET)
+#define MAP_IRAM_TO_DRAM(addr) (addr - SOC_I_D_OFFSET)
+
+// Region of memory accessible via DMA. See esp_ptr_dma_capable().
+#define SOC_DMA_LOW 0x3FC80000
+#define SOC_DMA_HIGH 0x3FCE0000
+
+// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
+#define SOC_BYTE_ACCESSIBLE_LOW 0x3FC80000
+#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000
+
+//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
+//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
+#define SOC_MEM_INTERNAL_LOW 0x3FC80000
+#define SOC_MEM_INTERNAL_HIGH 0x3FCE0000
+
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+
+// Region of address space that holds peripherals
+#define SOC_PERIPHERAL_LOW 0x60000000
+#define SOC_PERIPHERAL_HIGH 0x60100000
+
+// Debug region, not used by software
+#define SOC_DEBUG_LOW 0x20000000
+#define SOC_DEBUG_HIGH 0x28000000
+
+// Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START 0x3fcde710
+#define SOC_ROM_STACK_SIZE 0x2000

src/target/esp32c3/include/soc/soc_caps.h

@@ -0,0 +1,12 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+/* Capabilities */
+
+#define SOC_RTC_FAST_MEM_SUPPORTED 1
+#define SOC_RTC_MEM_SUPPORTED 1

src/target/esp32c5/include/soc/soc.h

@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+/* Overall memory map */
+#define SOC_IROM_LOW 0x42000000
+#define SOC_IROM_HIGH 0x44000000
+#define SOC_EXTRAM_DATA_LOW 0x42000000
+#define SOC_EXTRAM_DATA_HIGH 0x44000000
+#define SOC_DROM_LOW SOC_IROM_LOW
+#define SOC_DROM_HIGH SOC_IROM_HIGH
+#define SOC_IROM_MASK_LOW 0x40000000
+#define SOC_IROM_MASK_HIGH 0x40050000
+#define SOC_DROM_MASK_LOW 0x40000000
+#define SOC_DROM_MASK_HIGH 0x40050000
+#define SOC_IRAM_LOW 0x40800000
+#define SOC_IRAM_HIGH 0x40860000
+#define SOC_DRAM_LOW 0x40800000
+#define SOC_DRAM_HIGH 0x40860000
+#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C5 only has 16k LP memory
+#define SOC_RTC_IRAM_HIGH 0x50004000
+#define SOC_RTC_DRAM_LOW 0x50000000
+#define SOC_RTC_DRAM_HIGH 0x50004000
+#define SOC_RTC_DATA_LOW 0x50000000
+#define SOC_RTC_DATA_HIGH 0x50004000
+
+//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
+#define SOC_DIRAM_IRAM_LOW 0x40800000
+#define SOC_DIRAM_IRAM_HIGH 0x40860000
+#define SOC_DIRAM_DRAM_LOW 0x40800000
+#define SOC_DIRAM_DRAM_HIGH 0x40860000
+
+#define MAP_DRAM_TO_IRAM(addr) (addr)
+#define MAP_IRAM_TO_DRAM(addr) (addr)
+
+// Region of memory accessible via DMA. See esp_ptr_dma_capable().
+#define SOC_DMA_LOW 0x40800000
+#define SOC_DMA_HIGH 0x40860000
+
+// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
+#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000
+#define SOC_BYTE_ACCESSIBLE_HIGH 0x40860000
+
+//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
+//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
+#define SOC_MEM_INTERNAL_LOW 0x40800000
+#define SOC_MEM_INTERNAL_HIGH 0x40860000
+#define SOC_MEM_INTERNAL_LOW1 0x40800000
+#define SOC_MEM_INTERNAL_HIGH1 0x40860000
+
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IROM_HIGH - SOC_IROM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+
+// Region of address space that holds peripherals
+#define SOC_PERIPHERAL_LOW 0x60000000
+#define SOC_PERIPHERAL_HIGH 0x60100000
+
+// CPU sub-system region, contains interrupt config registers
+#define SOC_CPU_SUBSYSTEM_LOW 0x20000000
+#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
+
+// Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START 0x4085e5a0
+#define SOC_ROM_STACK_SIZE 0x2000

src/target/esp32c5/include/soc/soc_caps.h

@@ -0,0 +1,12 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+/* Capabilities */
+
+#define SOC_RTC_FAST_MEM_SUPPORTED 1
+#define SOC_RTC_MEM_SUPPORTED 1

src/target/esp32c6/include/soc/soc.h

@@ -0,0 +1,67 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+#define SOC_MMU_PAGE_SIZE 0x8000
+
+/* Overall memory map */
+#define SOC_IROM_LOW 0x42000000
+#define SOC_IROM_HIGH (SOC_IROM_LOW + (SOC_MMU_PAGE_SIZE<<8))
+#define SOC_DROM_LOW SOC_IROM_LOW
+#define SOC_DROM_HIGH SOC_IROM_HIGH
+#define SOC_IROM_MASK_LOW 0x40000000
+#define SOC_IROM_MASK_HIGH 0x40050000
+#define SOC_DROM_MASK_LOW 0x40000000
+#define SOC_DROM_MASK_HIGH 0x40050000
+#define SOC_IRAM_LOW 0x40800000
+#define SOC_IRAM_HIGH 0x40880000
+#define SOC_DRAM_LOW 0x40800000
+#define SOC_DRAM_HIGH 0x40880000
+#define SOC_RTC_IRAM_LOW 0x50000000 // ESP32-C6 only has 16k LP memory
+#define SOC_RTC_IRAM_HIGH 0x50004000
+#define SOC_RTC_DRAM_LOW 0x50000000
+#define SOC_RTC_DRAM_HIGH 0x50004000
+#define SOC_RTC_DATA_LOW 0x50000000
+#define SOC_RTC_DATA_HIGH 0x50004000
+
+//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
+#define SOC_DIRAM_IRAM_LOW 0x40800000
+#define SOC_DIRAM_IRAM_HIGH 0x40880000
+#define SOC_DIRAM_DRAM_LOW 0x40800000
+#define SOC_DIRAM_DRAM_HIGH 0x40880000
+
+#define MAP_DRAM_TO_IRAM(addr) (addr)
+#define MAP_IRAM_TO_DRAM(addr) (addr)
+
+// Region of memory accessible via DMA. See esp_ptr_dma_capable().
+#define SOC_DMA_LOW 0x40800000
+#define SOC_DMA_HIGH 0x40880000
+
+// Region of RAM that is byte-accessible. See esp_ptr_byte_accessible().
+#define SOC_BYTE_ACCESSIBLE_LOW 0x40800000
+#define SOC_BYTE_ACCESSIBLE_HIGH 0x40880000
+
+//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
+//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
+#define SOC_MEM_INTERNAL_LOW 0x40800000
+#define SOC_MEM_INTERNAL_HIGH 0x40880000
+#define SOC_MEM_INTERNAL_LOW1 0x40800000
+#define SOC_MEM_INTERNAL_HIGH1 0x40880000
+
+#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_IRAM_HIGH - SOC_IRAM_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
+
+// Region of address space that holds peripherals
+#define SOC_PERIPHERAL_LOW 0x60000000
+#define SOC_PERIPHERAL_HIGH 0x60100000
+
+// CPU sub-system region, contains interrupt config registers
+#define SOC_CPU_SUBSYSTEM_LOW 0x20000000
+#define SOC_CPU_SUBSYSTEM_HIGH 0x30000000
+
+// Start (highest address) of ROM boot stack, only relevant during early boot
+#define SOC_ROM_STACK_START 0x4087e610
+#define SOC_ROM_STACK_SIZE 0x2000

src/target/esp32c6/include/soc/soc_caps.h

@@ -0,0 +1,12 @@
+/*
+ * SPDX-FileCopyrightText: 2025 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0 OR MIT
+ */
+
+#pragma once
+
+/* Capabilities */
+
+#define SOC_RTC_FAST_MEM_SUPPORTED 1
+#define SOC_RTC_MEM_SUPPORTED 1