|
| 1 | +import { ESPLoader } from "../esploader"; |
| 2 | +import { ESP32C6ROM } from "./esp32c6"; |
| 3 | +import ESP32C5_STUB from "./stub_flasher/stub_flasher_32c5.json"; |
| 4 | + |
| 5 | +export class ESP32C5ROM extends ESP32C6ROM { |
| 6 | + public CHIP_NAME = "ESP32-C5"; |
| 7 | + public IMAGE_CHIP_ID = 23; |
| 8 | + |
| 9 | + public EFUSE_BASE = 0x600b4800; |
| 10 | + public EFUSE_BLOCK1_ADDR = this.EFUSE_BASE + 0x044; |
| 11 | + public MAC_EFUSE_REG = this.EFUSE_BASE + 0x044; |
| 12 | + public UART_CLKDIV_REG = 0x60000014; |
| 13 | + |
| 14 | + public TEXT_START = ESP32C5_STUB.text_start; |
| 15 | + public ENTRY = ESP32C5_STUB.entry; |
| 16 | + public DATA_START = ESP32C5_STUB.data_start; |
| 17 | + public ROM_DATA = ESP32C5_STUB.data; |
| 18 | + public ROM_TEXT = ESP32C5_STUB.text; |
| 19 | + |
| 20 | + public EFUSE_RD_REG_BASE = this.EFUSE_BASE + 0x030; // BLOCK0 read base address |
| 21 | + |
| 22 | + public EFUSE_PURPOSE_KEY0_REG = this.EFUSE_BASE + 0x34; |
| 23 | + public EFUSE_PURPOSE_KEY0_SHIFT = 24; |
| 24 | + public EFUSE_PURPOSE_KEY1_REG = this.EFUSE_BASE + 0x34; |
| 25 | + public EFUSE_PURPOSE_KEY1_SHIFT = 28; |
| 26 | + public EFUSE_PURPOSE_KEY2_REG = this.EFUSE_BASE + 0x38; |
| 27 | + public EFUSE_PURPOSE_KEY2_SHIFT = 0; |
| 28 | + public EFUSE_PURPOSE_KEY3_REG = this.EFUSE_BASE + 0x38; |
| 29 | + public EFUSE_PURPOSE_KEY3_SHIFT = 4; |
| 30 | + public EFUSE_PURPOSE_KEY4_REG = this.EFUSE_BASE + 0x38; |
| 31 | + public EFUSE_PURPOSE_KEY4_SHIFT = 8; |
| 32 | + public EFUSE_PURPOSE_KEY5_REG = this.EFUSE_BASE + 0x38; |
| 33 | + public EFUSE_PURPOSE_KEY5_SHIFT = 12; |
| 34 | + |
| 35 | + public EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_REG = this.EFUSE_RD_REG_BASE; |
| 36 | + public EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT = 1 << 20; |
| 37 | + |
| 38 | + public EFUSE_SPI_BOOT_CRYPT_CNT_REG = this.EFUSE_BASE + 0x034; |
| 39 | + public EFUSE_SPI_BOOT_CRYPT_CNT_MASK = 0x7 << 18; |
| 40 | + |
| 41 | + public EFUSE_SECURE_BOOT_EN_REG = this.EFUSE_BASE + 0x038; |
| 42 | + public EFUSE_SECURE_BOOT_EN_MASK = 1 << 20; |
| 43 | + |
| 44 | + public IROM_MAP_START = 0x42000000; |
| 45 | + public IROM_MAP_END = 0x42800000; |
| 46 | + public DROM_MAP_START = 0x42800000; |
| 47 | + public DROM_MAP_END = 0x43000000; |
| 48 | + |
| 49 | + public PCR_SYSCLK_CONF_REG = 0x60096110; |
| 50 | + public PCR_SYSCLK_XTAL_FREQ_V = 0x7f << 24; |
| 51 | + public PCR_SYSCLK_XTAL_FREQ_S = 24; |
| 52 | + |
| 53 | + public XTAL_CLK_DIVIDER = 1; |
| 54 | + |
| 55 | + public UARTDEV_BUF_NO = 0x4085f51c; // Variable in ROM .bss which indicates the port in use |
| 56 | + |
| 57 | + // Magic value for ESP32C5 |
| 58 | + public CHIP_DETECT_MAGIC_VALUE = [0x1101406f]; |
| 59 | + |
| 60 | + public FLASH_FREQUENCY = { |
| 61 | + "80m": 0xf, |
| 62 | + "40m": 0x0, |
| 63 | + "20m": 0x2, |
| 64 | + }; |
| 65 | + |
| 66 | + public MEMORY_MAP = [ |
| 67 | + [0x00000000, 0x00010000, "PADDING"], |
| 68 | + [0x42800000, 0x43000000, "DROM"], |
| 69 | + [0x40800000, 0x40860000, "DRAM"], |
| 70 | + [0x40800000, 0x40860000, "BYTE_ACCESSIBLE"], |
| 71 | + [0x4003a000, 0x40040000, "DROM_MASK"], |
| 72 | + [0x40000000, 0x4003a000, "IROM_MASK"], |
| 73 | + [0x42000000, 0x42800000, "IROM"], |
| 74 | + [0x40800000, 0x40860000, "IRAM"], |
| 75 | + [0x50000000, 0x50004000, "RTC_IRAM"], |
| 76 | + [0x50000000, 0x50004000, "RTC_DRAM"], |
| 77 | + [0x600fe000, 0x60100000, "MEM_INTERNAL2"], |
| 78 | + ]; |
| 79 | + |
| 80 | + UF2_FAMILY_ID = 0xf71c0343; |
| 81 | + |
| 82 | + EFUSE_MAX_KEY = 5; |
| 83 | + KEY_PURPOSES = { |
| 84 | + 0: "USER/EMPTY", |
| 85 | + 1: "ECDSA_KEY", |
| 86 | + 2: "XTS_AES_256_KEY_1", |
| 87 | + 3: "XTS_AES_256_KEY_2", |
| 88 | + 4: "XTS_AES_128_KEY", |
| 89 | + 5: "HMAC_DOWN_ALL", |
| 90 | + 6: "HMAC_DOWN_JTAG", |
| 91 | + 7: "HMAC_DOWN_DIGITAL_SIGNATURE", |
| 92 | + 8: "HMAC_UP", |
| 93 | + 9: "SECURE_BOOT_DIGEST0", |
| 94 | + 10: "SECURE_BOOT_DIGEST1", |
| 95 | + 11: "SECURE_BOOT_DIGEST2", |
| 96 | + 12: "KM_INIT_KEY", |
| 97 | + }; |
| 98 | + |
| 99 | + public async getPkgVersion(loader: ESPLoader): Promise<number> { |
| 100 | + const numWord = 2; |
| 101 | + return ((await loader.readReg(this.EFUSE_BLOCK1_ADDR + 4 * numWord)) >> 26) & 0x07; |
| 102 | + } |
| 103 | + |
| 104 | + public async getMinorChipVersion(loader: ESPLoader): Promise<number> { |
| 105 | + const numWord = 2; |
| 106 | + return ((await loader.readReg(this.EFUSE_BLOCK1_ADDR + 4 * numWord)) >> 0) & 0x0f; |
| 107 | + } |
| 108 | + |
| 109 | + public async getMajorChipVersion(loader: ESPLoader): Promise<number> { |
| 110 | + const numWord = 2; |
| 111 | + return ((await loader.readReg(this.EFUSE_BLOCK1_ADDR + 4 * numWord)) >> 4) & 0x03; |
| 112 | + } |
| 113 | + |
| 114 | + public async getChipDescription(loader: ESPLoader): Promise<string> { |
| 115 | + const pkgVer = await this.getPkgVersion(loader); |
| 116 | + let desc: string; |
| 117 | + if (pkgVer === 0) { |
| 118 | + desc = "ESP32-C5"; |
| 119 | + } else { |
| 120 | + desc = "unknown ESP32-C5"; |
| 121 | + } |
| 122 | + const majorRev = await this.getMajorChipVersion(loader); |
| 123 | + const minorRev = await this.getMinorChipVersion(loader); |
| 124 | + return `${desc} (revision v${majorRev}.${minorRev})`; |
| 125 | + } |
| 126 | + |
| 127 | + public async getCrystalFreq(loader: ESPLoader): Promise<number> { |
| 128 | + // The crystal detection algorithm of ESP32/ESP8266 |
| 129 | + // works for ESP32-C5 as well. |
| 130 | + const uartDiv = (await loader.readReg(this.UART_CLKDIV_REG)) & this.UART_CLKDIV_MASK; |
| 131 | + const etsXtal = (loader.transport.baudrate * uartDiv) / 1000000 / this.XTAL_CLK_DIVIDER; |
| 132 | + let normXtal; |
| 133 | + if (etsXtal > 45) { |
| 134 | + normXtal = 48; |
| 135 | + } else if (etsXtal > 33) { |
| 136 | + normXtal = 40; |
| 137 | + } else { |
| 138 | + normXtal = 26; |
| 139 | + } |
| 140 | + if (Math.abs(normXtal - etsXtal) > 1) { |
| 141 | + loader.info("WARNING: Unsupported crystal in use"); |
| 142 | + } |
| 143 | + return normXtal; |
| 144 | + } |
| 145 | + |
| 146 | + public async getCrystalFreqRomExpect(loader: ESPLoader) { |
| 147 | + return ( |
| 148 | + ((await loader.readReg(this.PCR_SYSCLK_CONF_REG)) & this.PCR_SYSCLK_XTAL_FREQ_V) >> this.PCR_SYSCLK_XTAL_FREQ_S |
| 149 | + ); |
| 150 | + } |
| 151 | +} |
0 commit comments