ESP32C2、ESP32C3，efuse address error (ESPTOOL-1263)

[mehuia]

Operating System

none

Esptool Version

lastes

Python Version

3.6

Full Esptool Command Line that Was Run

none

Esptool Output

none

What is the Expected Behaviour?

No response

More Information

I noticed that the documentation for esp32C2 and esp32C3 is inconsistent with the Python source code. The base address for efuse is different in the two cases.
Could you please provide a revised document? I need the correct base address and the correct offset address. Otherwise, my chip will write incorrect efuse data.

Other Steps to Reproduce

No response

[github-actions]

Hi @mehuia! Please be aware that (1) the following suggestions are generated by a bot and haven't been fact-checked by Espressif Systems, (2) burning eFuses and enabling security features are irreversible operations and can damage your ESP32 device. We hope that this message will help you until an Espressif Engineer looks at your issue.

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You are right to be careful here: using the wrong base/offset for eFuse will corrupt irreversible data.

From the available technical docs, we can summarize the situation like this:

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1. ESP32‑C3 eFuse base and offsets

For ESP32‑C3, the TRM gives offsets relative to the eFuse controller base address. The base address itself is defined in the System & Memory chapter (Table 3.3‑3), and all eFuse registers in Chapter 4 use offsets from that base. For example, the read‑data registers are listed as:

• EFUSE_RD_SYS_PART1_DATA0_REG – offset 0x005C
• EFUSE_RD_SYS_PART1_DATA1_REG – offset 0x0060
• … up to EFUSE_RD_SYS_PART1_DATA7_REG – offset 0x0078
• EFUSE_RD_USR_DATA0_REG – offset 0x007C
• … up to EFUSE_RD_USR_DATA7_REG – offset 0x0098 [ESP32‑C3 TRM reg summary].

Programming data registers are similarly defined:

• EFUSE_PGM_DATA0_REG – offset 0x0000
• … up to EFUSE_PGM_DATA7_REG – offset 0x001C
• RS/check registers at 0x0020–0x0028 [ESP32‑C3 TRM reg summary].

Control/status registers (clock, command, timing, etc.) are also given as offsets:

• EFUSE_CLK_REG – 0x01C8
• EFUSE_CONF_REG – 0x01CC
• EFUSE_CMD_REG – 0x01D4
• EFUSE_STATUS_REG – 0x01D0
• Interrupt and timing registers at 0x01D8–0x01F4
• EFUSE_DATE_REG – 0x01FC [ESP32‑C3 TRM reg summary].

So for ESP32‑C3, the layout and offsets in the TRM are internally consistent; the only thing you must add is the SoC‑specific eFuse base address from the System & Memory chapter.

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2. ESP32‑C2 eFuse base and offsets

For ESP32‑C2, the ESP‑IDF eFuse Manager documentation describes the block structure (4 blocks × 256 bits, each block = 8 × 32‑bit registers) and which blocks are system vs. user/keys, but it does not give the low‑level base address or per‑register offsets in this document. [ESP32‑C2 eFuse Manager]

The correct low‑level base and offsets for ESP32‑C2 must be taken from the ESP8684 / ESP32‑C2 Technical Reference Manual, which is only linked from the eFuse Manager page and not reproduced in the knowledge I have:

“For more details, see ESP32‑C2 Technical Reference Manual > eFuse Controller (eFuse).” [ESP32‑C2 eFuse Manager]

Because that TRM content is not included in the provided sources, I cannot confirm the exact ESP32‑C2 eFuse base address or per‑register offsets from here.

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3. Why esptool may look “different”

esptool does not program eFuses by directly poking the eFuse controller registers from the host; instead, it talks to the ROM bootloader (or flasher stub) over the serial protocol, and the ROM/stub code on the chip accesses the eFuse hardware. [Esptool intro]

That means:

• Any eFuse base/offset constants you see in esptool Python code are usually for decoding/encoding fields, not for doing raw MMIO from the PC.
• The authoritative mapping of eFuse bits to addresses is the SoC TRM + ESP‑IDF eFuse tables, not the Python code.

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4. Risk and recommendation

Because eFuses are one‑time programmable, using guessed or inconsistent base/offsets is dangerous. From the information available here:

• ESP32‑C3: the offsets in the TRM are correct and consistent; combine them with the eFuse base address from the System & Memory chapter of the ESP32‑C3 TRM. [ESP32‑C3 TRM reg summary]
• ESP32‑C2: the block structure is documented, but the exact base and offsets are only in the ESP32‑C2/ESP8684 TRM, which is not fully included in these sources, so I cannot quote them here. [ESP32‑C2 eFuse Manager]

Given your concern about a mismatch between documentation and Python source, the safest path is:

1. For each chip (ESP32‑C2 and ESP32‑C3), take the eFuse base address from the “System and Memory” chapter of the corresponding TRM.
2. Use the eFuse register offsets from the “eFuse Controller” chapter of that same TRM.
3. Treat any apparent difference in esptool Python as a tooling/decoding detail, not as the hardware truth.
4. If you still see a concrete inconsistency (e.g., a specific register offset that differs between TRM and esptool), please report that exact symbol and address to Espressif so it can be checked and, if needed, corrected in the docs.

From the knowledge available here I cannot provide a corrected ESP32‑C2 base address or confirm a specific error in the public documentation; only the ESP32‑C3 offsets are clearly visible and consistent.

[KonstantinKondrashov]

Hello @mehuia!
The doc has a wrong offset; 0x60008800 is correct for C3 and C2.
https://github.com/espressif/esp-idf/blob/master/components/soc/esp32c3/register/soc/reg_base.h#L34.

The docs will be updated, thanks for noticing it.