[Xtensa] Alignment fix

Author: sstefan1

.gitignore

@@ -31,6 +31,7 @@
 /*/build-*
 /_build
 /_dist
+/dbg
 
 #==============================================================================#
 # Explicit files to ignore (only matches one).

llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp

@@ -62,6 +62,9 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF,
 
   if (STI.isWinABI()) {
     StackSize += 32;
+    uint64_t MaxAlignment = MFI.getMaxAlign().value();
+    if(MaxAlignment > 32)
+      StackSize += MaxAlignment;
 
     if (StackSize <= 32760) {
       BuildMI(MBB, MBBI, DL, TII.get(Xtensa::ENTRY))
@@ -83,6 +86,28 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF,
       BuildMI(MBB, MBBI, DL, TII.get(Xtensa::MOVSP), SP).addReg(TmpReg);
     }
 
+    // Calculate how much is needed to have the correct alignment.
+    // Change offset to: alignment + difference.
+    // For example, in case of alignment of 128:
+    // diff_to_128_aligned_address = (128 - (SP & 127))
+    // new_offset = 128 + diff_to_128_aligned_address
+    // This is safe to do because we increased the stack size by MaxAlignment.
+    unsigned Reg, RegMisAlign;
+    if (MaxAlignment > 32){
+      TII.loadImmediate(MBB, MBBI, &RegMisAlign, MaxAlignment - 1);
+      TII.loadImmediate(MBB, MBBI, &Reg, MaxAlignment);
+      BuildMI(MBB, MBBI, DL, TII.get(Xtensa::AND))
+          .addReg(RegMisAlign, RegState::Define)
+          .addReg(FP)
+          .addReg(RegMisAlign);
+      BuildMI(MBB, MBBI, DL, TII.get(Xtensa::SUB), RegMisAlign)
+          .addReg(Reg)
+          .addReg(RegMisAlign);
+      BuildMI(MBB, MBBI, DL, TII.get(Xtensa::ADD), SP)
+          .addReg(SP)
+          .addReg(RegMisAlign, RegState::Kill);
+    }
+
     // Store FP register in A8, because FP may be used to pass function
     // arguments
     if (XtensaFI->isSaveFrameRegister()) {

llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp

@@ -119,20 +119,21 @@ bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
   int64_t Offset =
       SPOffset + (int64_t)StackSize + MI.getOperand(FIOperandNum + 1).getImm();
 
+  uint64_t Alignment = MF.getFrameInfo().getObjectAlign(FrameIndex).value();
   bool Valid = isValidAddrOffset(MI, Offset);
 
   // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
   // field.
   if (!MI.isDebugValue() && !Valid) {
     MachineBasicBlock &MBB = *MI.getParent();
     DebugLoc DL = II->getDebugLoc();
-    unsigned ADD = Xtensa::ADD;
     unsigned Reg;
     const XtensaInstrInfo &TII = *static_cast<const XtensaInstrInfo *>(
         MBB.getParent()->getSubtarget().getInstrInfo());
 
     TII.loadImmediate(MBB, II, &Reg, Offset);
-    BuildMI(MBB, II, DL, TII.get(ADD), Reg)
+
+    BuildMI(MBB, II, DL, TII.get(Xtensa::ADD), Reg)
         .addReg(FrameReg)
         .addReg(Reg, RegState::Kill);
 

llvm/test/CodeGen/Xtensa/aligned_alloc.ll

@@ -0,0 +1,29 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=xtensa -O0 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefix=XTENSA
+
+define i8 @loadi8_128(i8 %a) {
+; XTENSA-LABEL: loadi8_128:
+; XTENSA:         entry a1, 416
+; XTENSA-NEXT:    movi a8, 127
+; XTENSA-NEXT:    movi a9, 128
+; XTENSA-NEXT:    and a8, a1, a8
+; XTENSA-NEXT:    sub a8, a9, a8
+; XTENSA-NEXT:    add.n a1, a1, a8
+; XTENSA-NEXT:    movi a8, 128
+; XTENSA-NEXT:    add.n a8, a1, a8
+; XTENSA-NEXT:    addi a10, a8, 0
+; XTENSA-NEXT:    movi.n a11, 0
+; XTENSA-NEXT:    movi.n a12, 64
+; XTENSA-NEXT:    l32r a8, .LCPI0_0
+; XTENSA-NEXT:    callx8 a8
+; XTENSA-NEXT:    l8ui a2, a1, 128
+; XTENSA-NEXT:    retw.n
+    %aligned = alloca i8, align 128
+    call void @llvm.memset.p0.i64(ptr noundef nonnull align 64 dereferenceable(64) %aligned, i8 0, i64 64, i1 false)
+    %1 = load i8, ptr %aligned, align 128
+    ret i8 %1
+}
+
+; Function Attrs: nocallback nofree nounwind willreturn memory(argmem: write)
+declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1 immarg)