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[Test] add LoopVectorizeExtractor testcase
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‎llvm/test/CodeGen/RISCV/esp32p4/loopVectorizeExtractor/dsps_add_s16_ansi_instcombine.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -S -mtriple=riscv32-esp-unknown-elf < %s | FileCheck %s
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; Function Attrs: nofree norecurse nosync nounwind memory(argmem: readwrite)
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define dso_local range(i32 0, 458756) i32 @dsps_add_s16_ansi(ptr noundef readonly %input1, ptr noundef readonly %input2, ptr noundef writeonly %output, i32 noundef %len, i32 noundef %step1, i32 noundef %step2, i32 noundef %step_out, i32 noundef %shift) local_unnamed_addr #0 {
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; CHECK-LABEL: define dso_local range(i32 0, 458756) i32 @dsps_add_s16_ansi(
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; CHECK-SAME: ptr noundef readonly [[INPUT1:%.*]], ptr noundef readonly [[INPUT2:%.*]], ptr noundef writeonly [[OUTPUT:%.*]], i32 noundef [[LEN:%.*]], i32 noundef [[STEP1:%.*]], i32 noundef [[STEP2:%.*]], i32 noundef [[STEP_OUT:%.*]], i32 noundef [[SHIFT:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr [[INPUT1]], null
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; CHECK-NEXT: [[CMP1:%.*]] = icmp eq ptr [[INPUT2]], null
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; CHECK-NEXT: [[OR_COND:%.*]] = or i1 [[CMP]], [[CMP1]]
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; CHECK-NEXT: [[CMP4:%.*]] = icmp eq ptr [[OUTPUT]], null
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; CHECK-NEXT: [[OR_COND21:%.*]] = or i1 [[OR_COND]], [[CMP4]]
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; CHECK-NEXT: br i1 [[OR_COND21]], label %[[RETURN:.*]], label %[[FOR_COND_PREHEADER:.*]]
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; CHECK: [[FOR_COND_PREHEADER]]:
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; CHECK-NEXT: [[CMP722:%.*]] = icmp sgt i32 [[LEN]], 0
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; CHECK-NEXT: br i1 [[CMP722]], label %[[FOR_BODY_PREHEADER:.*]], label %[[RETURN]]
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; CHECK: [[FOR_BODY_PREHEADER]]:
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; CHECK-NEXT: [[STRIDE_IS_ONE:%.*]] = icmp eq i32 [[STEP_OUT]], 1
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; CHECK-NEXT: [[STRIDE_IS_ONE1:%.*]] = icmp eq i32 [[STEP2]], 1
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; CHECK-NEXT: [[TMP0:%.*]] = and i1 [[STRIDE_IS_ONE]], [[STRIDE_IS_ONE1]]
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; CHECK-NEXT: [[STRIDE_IS_ONE2:%.*]] = icmp eq i32 [[STEP1]], 1
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; CHECK-NEXT: [[TMP1:%.*]] = and i1 [[TMP0]], [[STRIDE_IS_ONE2]]
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; CHECK-NEXT: br i1 [[TMP1]], label %[[FAST_PATH_PREHEADER:.*]], label %[[FOR_BODY:.*]]
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; CHECK: [[FAST_PATH_PREHEADER]]:
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; CHECK-NEXT: br label %[[FOR_BODY_FAST:.*]]
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; CHECK: [[FOR_BODY_FAST]]:
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; CHECK-NEXT: [[I_023_FAST:%.*]] = phi i32 [ [[INC_FAST:%.*]], %[[FOR_BODY_FAST]] ], [ 0, %[[FAST_PATH_PREHEADER]] ]
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; CHECK-NEXT: [[ARRAYIDX_FAST:%.*]] = getelementptr inbounds i16, ptr [[INPUT1]], i32 [[I_023_FAST]]
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; CHECK-NEXT: [[TMP32:%.*]] = load i16, ptr [[ARRAYIDX_FAST]], align 2, !tbaa [[TBAA6:![0-9]+]]
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; CHECK-NEXT: [[CONV_FAST:%.*]] = sext i16 [[TMP32]] to i32
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; CHECK-NEXT: [[ARRAYIDX9_FAST:%.*]] = getelementptr inbounds i16, ptr [[INPUT2]], i32 [[I_023_FAST]]
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; CHECK-NEXT: [[TMP33:%.*]] = load i16, ptr [[ARRAYIDX9_FAST]], align 2, !tbaa [[TBAA6]]
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; CHECK-NEXT: [[CONV10_FAST:%.*]] = sext i16 [[TMP33]] to i32
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; CHECK-NEXT: [[ADD_FAST:%.*]] = add nsw i32 [[CONV10_FAST]], [[CONV_FAST]]
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; CHECK-NEXT: [[SHR_FAST:%.*]] = ashr i32 [[ADD_FAST]], [[SHIFT]]
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; CHECK-NEXT: [[CONV11_FAST:%.*]] = trunc i32 [[SHR_FAST]] to i16
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; CHECK-NEXT: [[ARRAYIDX13_FAST:%.*]] = getelementptr inbounds i16, ptr [[OUTPUT]], i32 [[I_023_FAST]]
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; CHECK-NEXT: store i16 [[CONV11_FAST]], ptr [[ARRAYIDX13_FAST]], align 2, !tbaa [[TBAA6]]
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; CHECK-NEXT: [[INC_FAST]] = add nuw nsw i32 [[I_023_FAST]], 1
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; CHECK-NEXT: [[EXITCOND_NOT_FAST:%.*]] = icmp eq i32 [[INC_FAST]], [[LEN]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT_FAST]], label %[[RETURN_LOOPEXIT:.*]], label %[[FOR_BODY_FAST]], !llvm.loop [[LOOP10:![0-9]+]]
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; CHECK: [[FOR_BODY]]:
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; CHECK-NEXT: [[I_023:%.*]] = phi i32 [ [[INC:%.*]], %[[FOR_BODY]] ], [ 0, %[[FOR_BODY_PREHEADER]] ]
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; CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[I_023]], [[STEP1]]
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; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, ptr [[INPUT1]], i32 [[MUL]]
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; CHECK-NEXT: [[TMP34:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !tbaa [[TBAA6]]
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; CHECK-NEXT: [[CONV:%.*]] = sext i16 [[TMP34]] to i32
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; CHECK-NEXT: [[MUL8:%.*]] = mul nsw i32 [[I_023]], [[STEP2]]
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; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i16, ptr [[INPUT2]], i32 [[MUL8]]
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; CHECK-NEXT: [[TMP35:%.*]] = load i16, ptr [[ARRAYIDX9]], align 2, !tbaa [[TBAA6]]
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; CHECK-NEXT: [[CONV10:%.*]] = sext i16 [[TMP35]] to i32
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; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV10]], [[CONV]]
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; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[ADD]], [[SHIFT]]
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; CHECK-NEXT: [[CONV11:%.*]] = trunc i32 [[SHR]] to i16
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; CHECK-NEXT: [[MUL12:%.*]] = mul nsw i32 [[I_023]], [[STEP_OUT]]
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; CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i16, ptr [[OUTPUT]], i32 [[MUL12]]
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; CHECK-NEXT: store i16 [[CONV11]], ptr [[ARRAYIDX13]], align 2, !tbaa [[TBAA6]]
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; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[I_023]], 1
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; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC]], [[LEN]]
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; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label %[[RETURN_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP10]]
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; CHECK: [[RETURN_LOOPEXIT]]:
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; CHECK-NEXT: br label %[[RETURN]]
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; CHECK: [[RETURN]]:
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; CHECK-NEXT: [[RETVAL_0:%.*]] = phi i32 [ 458755, %[[ENTRY]] ], [ 0, %[[FOR_COND_PREHEADER]] ], [ 0, %[[RETURN_LOOPEXIT]] ]
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; CHECK-NEXT: ret i32 [[RETVAL_0]]
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;
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entry:
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%cmp = icmp eq ptr %input1, null
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%cmp1 = icmp eq ptr %input2, null
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%or.cond = or i1 %cmp, %cmp1
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%cmp4 = icmp eq ptr %output, null
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%or.cond21 = or i1 %or.cond, %cmp4
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br i1 %or.cond21, label %return, label %for.cond.preheader
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for.cond.preheader: ; preds = %entry
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%cmp722 = icmp sgt i32 %len, 0
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br i1 %cmp722, label %for.body.preheader, label %return
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for.body.preheader: ; preds = %for.cond.preheader
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%stride.is.one = icmp eq i32 %step_out, 1
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%stride.is.one1 = icmp eq i32 %step2, 1
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%0 = and i1 %stride.is.one, %stride.is.one1
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%stride.is.one2 = icmp eq i32 %step1, 1
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%1 = and i1 %0, %stride.is.one2
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br i1 %1, label %fast.path.preheader, label %for.body
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fast.path.preheader: ; preds = %for.body.preheader
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br label %for.body.fast
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for.body.fast: ; preds = %for.body.fast, %fast.path.preheader
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%i.023.fast = phi i32 [ %inc.fast, %for.body.fast ], [ 0, %fast.path.preheader ]
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%arrayidx.fast = getelementptr inbounds i16, ptr %input1, i32 %i.023.fast
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%2 = load i16, ptr %arrayidx.fast, align 2, !tbaa !6
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%conv.fast = sext i16 %2 to i32
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%arrayidx9.fast = getelementptr inbounds i16, ptr %input2, i32 %i.023.fast
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%3 = load i16, ptr %arrayidx9.fast, align 2, !tbaa !6
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%conv10.fast = sext i16 %3 to i32
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%add.fast = add nsw i32 %conv10.fast, %conv.fast
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%shr.fast = ashr i32 %add.fast, %shift
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%conv11.fast = trunc i32 %shr.fast to i16
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%arrayidx13.fast = getelementptr inbounds i16, ptr %output, i32 %i.023.fast
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store i16 %conv11.fast, ptr %arrayidx13.fast, align 2, !tbaa !6
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%inc.fast = add nuw nsw i32 %i.023.fast, 1
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%exitcond.not.fast = icmp eq i32 %inc.fast, %len
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br i1 %exitcond.not.fast, label %return.loopexit, label %for.body.fast, !llvm.loop !10
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for.body: ; preds = %for.body, %for.body.preheader
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%i.023 = phi i32 [ %inc, %for.body ], [ 0, %for.body.preheader ]
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%mul = mul nsw i32 %i.023, %step1
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%arrayidx = getelementptr inbounds i16, ptr %input1, i32 %mul
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%4 = load i16, ptr %arrayidx, align 2, !tbaa !6
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%conv = sext i16 %4 to i32
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%mul8 = mul nsw i32 %i.023, %step2
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%arrayidx9 = getelementptr inbounds i16, ptr %input2, i32 %mul8
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%5 = load i16, ptr %arrayidx9, align 2, !tbaa !6
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%conv10 = sext i16 %5 to i32
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%add = add nsw i32 %conv10, %conv
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%shr = ashr i32 %add, %shift
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%conv11 = trunc i32 %shr to i16
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%mul12 = mul nsw i32 %i.023, %step_out
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%arrayidx13 = getelementptr inbounds i16, ptr %output, i32 %mul12
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store i16 %conv11, ptr %arrayidx13, align 2, !tbaa !6
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%inc = add nuw nsw i32 %i.023, 1
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%exitcond.not = icmp eq i32 %inc, %len
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br i1 %exitcond.not, label %return.loopexit, label %for.body, !llvm.loop !10
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return.loopexit: ; preds = %for.body, %for.body.fast
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br label %return
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return: ; preds = %return.loopexit, %for.cond.preheader, %entry
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%retval.0 = phi i32 [ 458755, %entry ], [ 0, %for.cond.preheader ], [ 0, %return.loopexit ]
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ret i32 %retval.0
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}
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attributes #0 = { nofree norecurse nosync nounwind memory(argmem: readwrite) "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic-rv32" "target-features"="+32bit,+a,+c,+f,+m,+relax,+xesppie,+zca,+zcmp,+zicsr,+zifencei,+zmmul,-b,-d,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-h,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b" }
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!llvm.module.flags = !{!0, !1, !2, !4}
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!llvm.ident = !{!5}
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!0 = !{i32 1, !"wchar_size", i32 4}
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!1 = !{i32 1, !"target-abi", !"ilp32f"}
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!2 = !{i32 6, !"riscv-isa", !3}
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!3 = !{!"rv32i2p1_m2p0_a2p1_f2p2_c2p0_zicsr2p0_zifencei2p0_zmmul1p0_zca1p0_zcmp1p0_xesppie1p0"}
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!4 = !{i32 8, !"SmallDataLimit", i32 8}
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!5 = !{!"Espressif clang version 17.0.1 (https://gitlab.espressif.cn:6688/idf/llvm-project.git llvmorg-19.1.2-277-gbe3198f esp-18.1.2_20240912-657-ge1dc1cc esp-18.1.2_20240912-657-ge1dc1cc esp-18.1.2_20240912-685-g8c39bf5 llvmorg-19.1.2-280-g353ae76 llvmorg-19.1.2-280-g353ae76 llvmorg-19.1.2-280-g353ae76 llvmorg-19.1.2-280-g353ae76 llvmorg-19.1.2-280-g353ae76 llvmorg-19.1.2-280-g353ae76 esp-18.1.2_20240912-694-g4a14fa0 esp-18.1.2_20240912-694-g4a14fa0 llvmorg-19.1.2-280-g353ae76 llvmorg-19.1.2-280-g353ae76 llvmorg-19.1.2-282-gf0df22b llvmorg-19.1.2-282-g61f783f llvmorg-19.1.2-280-g353ae76 llvmorg-19.1.2-280-g353ae76 llvmorg-19.1.2-280-g353ae76 llvmorg-19.1.2-289-g6ab7981 llvmorg-19.1.2-294-ga687ee8 llvmorg-19.1.2-282-gded6180 llvmorg-19.1.2-295-gd6b9c67 llvmorg-19.1.2-296-g2bb38d3 llvmorg-19.1.2-302-gb46e43e llvmorg-19.1.2-282-g92c3b79 llvmorg-19.1.2-282-g92c3b79 llvmorg-19.1.2-282-g92c3b79 llvmorg-19.1.2-282-g92c3b79 llvmorg-19.1.2-282-g92c3b79 llvmorg-19.1.2-282-g92c3b79 llvmorg-19.1.2-282-ga193982 llvmorg-19.1.2-310-g012c995 llvmorg-19.1.2-373-g483ac18 llvmorg-19.1.2-373-g483ac18 llvmorg-19.1.2-373-g483ac18 esp-19.1.2_20250225-2-g2444a40 esp-19.1.2_20250225-2-g77f93cb esp-19.1.2_20250225-2-g77f93cb esp-19.1.2_20250225-2-g77f93cb esp-19.1.2_20250225-2-g77f93cb esp-19.1.2_20250225-2-g77f93cb esp-19.1.2_20250225-2-g77f93cb esp-19.1.2_20250225-2-g77f93cb esp-19.1.2_20250225-2-g77f93cb esp-19.1.2_20250225-2-g77f93cb esp-19.1.2_20250225-2-g5a99af4 esp-19.1.2_20250225-2-g5a99af4 esp-19.1.2_20250225-4-g6ad288c esp-19.1.2_20250225-2-g78646ff esp-19.1.2_20250312 esp-19.1.2_20250312 esp-19.1.2_20250312-1-gbfbef3f esp-19.1.2_20250225-3-g153f4c7 esp-19.1.2_20250312-2-gf1328c0 esp-19.1.2_20250312-1-ga44194f esp-19.1.2_20250312-2-g6ad288c esp-19.1.2_20250225-5-gabba736 esp-19.1.2_20250312-6-gea26128 esp-19.1.2_20250312-6-gea26128 esp-19.1.2_20250312-6-gea26128 esp-19.1.2_20250312-6-gea26128 esp-19.1.2_20250312-1-ge8e26d4 esp-19.1.2_20250225-6-g1102ab9 esp-19.1.2_20250312-1-ga44194f esp-19.1.2_20250312-1-gfaf5f34 esp-19.1.2_20250312-2-g912da7e esp-19.1.2_20250312-12-g40fcb86 esp-19.1.2_20250312-22-g150517d esp-19.1.2_20250312-36-g3725281 esp-19.1.2_20250312-36-g3725281 esp-19.1.2_20250312-37-gd7ad151 esp-19.1.2_20250312-43-g1fdfc46 esp-19.1.2_20250225-9-gbdf8145 esp-19.1.2_20250225-9-gbdf8145 esp-19.1.2_20250225-9-gbdf8145 esp-19.1.2_20250312-67-g1b9c1af esp-19.1.2_20250312-67-g1b9c1af esp-19.1.2_20250312-2-g590a30f esp-19.1.2_20250312-2-g590a30f esp-19.1.2_20250312-68-g65bae88 esp-19.1.2_20250312-68-g65bae88 llvmorg-19.1.2-286-g58c0b0a esp-19.1.2_20250312-75-gc8e87f2 esp-19.1.2_20250312-75-gc8e87f2 esp-19.1.2_20250312-75-gc8e87f2 esp-19.1.2_20250312-2-gaccea5b esp-19.1.2_20250312-79-g85b8bac esp-19.1.2_20250312-1-g5bd87a5 esp-19.1.2_20250312-2-g398f0e9 esp-19.1.2_20250312-2-gfa1159a esp-19.1.2_20250312 esp-19.1.2_20250312-1-g190f2f0 esp-19.1.2_20250312 esp-19.1.2_20250312 esp-19.1.2_20250312 esp-19.1.2_20250312 esp-19.1.2_20250312-1-gdb3618a esp-19.1.2_20250312-5-g53503ec esp-19.1.2_20250312-14-gbd1030c esp-19.1.2_20250312-14-gbd1030c esp-19.1.2_20250312-94-ga50fb83 esp-19.1.2_20250312-21-g2d4e527 esp-19.1.2_20250312-22-gd828f8c esp-19.1.2_20250312-25-ga0db53c esp-19.1.2_20250312-30-g872c496e esp-19.1.2_20250312-30-g872c496e esp-19.1.2_20250312-30-g872c496e esp-19.1.2_20250312-50-g36efec3 esp-19.1.2_20250312-49-g66c7bd3 esp-19.1.2_20250312-68-gef601b8 esp-19.1.2_20250312-84-g3338f1a esp-19.1.2_20250225-105-gfa4c43d esp-19.1.2_20250312-99-gcad4d17 esp-19.1.2_20250312-2-g7c53768 esp-19.1.2_20250312-2-g7c53768 esp-19.1.2_20250312-3-g77450217 esp-19.1.2_20250312-1-g0b10ac7 esp-19.1.2_20250312-1-g0b10ac7 esp-19.1.2_20250312-7-ge58b5b9 esp-19.1.2_20250312-7-ge58b5b9 esp-19.1.2_20250312-9-gf8d929c esp-19.1.2_20250312-9-gf8d929c esp-19.1.2_20250312-1-g0b10ac7 esp-19.1.2_20250312-14-gcc23a57 esp-19.1.2_20250312-15-gb030eec esp-19.1.2_20250312-16-g5e690f7 esp-19.1.2_20250312-18-g64518b8 esp-19.1.2_20250312-19-gf837620 esp-19.1.2_20250312-30-gce11723 esp-19.1.2_20250312-36-gc4a4385 esp-19.1.2_20250312-45-gb1f78a1 esp-19.1.2_20250312-45-gb1f78a1)"}
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!6 = !{!7, !7, i64 0}
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!7 = !{!"short", !8, i64 0}
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!8 = !{!"omnipotent char", !9, i64 0}
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!9 = !{!"Simple C/C++ TBAA"}
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!10 = distinct !{!10, !11}
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!11 = !{!"llvm.loop.mustprogress"}
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;.
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; CHECK: [[TBAA6]] = !{[[META7:![0-9]+]], [[META7]], i64 0}
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; CHECK: [[META7]] = !{!"short", [[META8:![0-9]+]], i64 0}
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; CHECK: [[META8]] = !{!"omnipotent char", [[META9:![0-9]+]], i64 0}
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; CHECK: [[META9]] = !{!"Simple C/C++ TBAA"}
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; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META11:![0-9]+]]}
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; CHECK: [[META11]] = !{!"llvm.loop.mustprogress"}
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;.

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