@@ -3416,7 +3416,7 @@ void DAGTypeLegalizer::SplitVecRes_PARTIAL_REDUCE_MLA(SDNode *N, SDValue &Lo,
34163416 SDValue Input2 = N->getOperand (2 );
34173417
34183418 SDValue AccLo, AccHi;
3419- std::tie (AccLo, AccHi) = DAG. SplitVector (Acc, DL );
3419+ GetSplitVector (Acc, AccLo, AccHi );
34203420 unsigned Opcode = N->getOpcode ();
34213421
34223422 // If the input types don't need splitting, just accumulate into the
@@ -3429,8 +3429,8 @@ void DAGTypeLegalizer::SplitVecRes_PARTIAL_REDUCE_MLA(SDNode *N, SDValue &Lo,
34293429
34303430 SDValue Input1Lo, Input1Hi;
34313431 SDValue Input2Lo, Input2Hi;
3432- std::tie (Input1Lo, Input1Hi) = DAG. SplitVector (Input1, DL );
3433- std::tie (Input2Lo, Input2Hi) = DAG. SplitVector (Input2, DL );
3432+ GetSplitVector (Input1, Input1Lo, Input1Hi );
3433+ GetSplitVector (Input2, Input2Lo, Input2Hi );
34343434 EVT ResultVT = AccLo.getValueType ();
34353435
34363436 Lo = DAG.getNode (Opcode, DL, ResultVT, AccLo, Input1Lo, Input2Lo);
@@ -4761,8 +4761,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_PARTIAL_REDUCE_MLA(SDNode *N) {
47614761
47624762 SDLoc DL (N);
47634763 SDValue Input1Lo, Input1Hi, Input2Lo, Input2Hi;
4764- std::tie (Input1Lo, Input1Hi) = DAG. SplitVector ( N->getOperand (1 ), DL );
4765- std::tie (Input2Lo, Input2Hi) = DAG. SplitVector ( N->getOperand (2 ), DL );
4764+ GetSplitVector ( N->getOperand (1 ), Input1Lo, Input1Hi );
4765+ GetSplitVector ( N->getOperand (2 ), Input2Lo, Input2Hi );
47664766 unsigned Opcode = N->getOpcode ();
47674767 EVT ResultVT = Acc.getValueType ();
47684768
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