esp-18.1.2_20240815
·
25 commits
to xtensa_release_18.1.2
since this release
Changes since esp-17.0.1_20240419:
Features:
- Upgraded LLVM ver to 18.1.2.
- [RISCV] Support for ESP32-P4 custom instructions in RISCV backend.
- [RISCV] Add support for user trap CSRs.
- [Xtensa] Added support for asm underscore prefix which prevents assembler from replacing instructions with their equivalents (single or multiple instructions) when it is applicable.