1+ {
2+ "$defs" : {
3+ "ResetStyle" : {
4+ "description" : " Flip-flop reset style." ,
5+ "enum" : [
6+ " sync_pos" ,
7+ " sync_neg" ,
8+ " async_pos" ,
9+ " async_neg"
10+ ],
11+ "title" : " ResetStyle" ,
12+ "type" : " string"
13+ },
14+ "corsair___generators__markdown__MarkdownGenerator__Config" : {
15+ "additionalProperties" : false ,
16+ "description" : " Configuration for the Markdown generator." ,
17+ "properties" : {
18+ "kind" : {
19+ "const" : " markdown" ,
20+ "default" : " markdown" ,
21+ "description" : " Generator kind discriminator." ,
22+ "title" : " Kind" ,
23+ "type" : " string"
24+ },
25+ "file_name" : {
26+ "default" : " regmap.md" ,
27+ "description" : " Name of the output file." ,
28+ "title" : " File Name" ,
29+ "type" : " string"
30+ },
31+ "title" : {
32+ "default" : " Register Map" ,
33+ "description" : " Document title." ,
34+ "title" : " Title" ,
35+ "type" : " string"
36+ },
37+ "print_images" : {
38+ "default" : false ,
39+ "description" : " Enable generating images for bit fields of a register." ,
40+ "title" : " Print Images" ,
41+ "type" : " boolean"
42+ },
43+ "image_dir" : {
44+ "default" : " img" ,
45+ "description" : " Directory for storing images." ,
46+ "format" : " path" ,
47+ "title" : " Image Dir" ,
48+ "type" : " string"
49+ },
50+ "print_conventions" : {
51+ "default" : true ,
52+ "description" : " Enable generating table with register access modes explained." ,
53+ "title" : " Print Conventions" ,
54+ "type" : " boolean"
55+ },
56+ "wavedrom" : {
57+ "$ref" : " #/$defs/corsair___generators__wavedrom__WaveDromGenerator__Config" ,
58+ "default" : {
59+ "kind" : " wavedrom" ,
60+ "vspace" : 80 ,
61+ "hspace" : 800 ,
62+ "lanes" : 1 ,
63+ "bits" : 32 ,
64+ "hflip" : false ,
65+ "vflip" : false ,
66+ "fontsize" : 14 ,
67+ "fontfamily" : " sans-serif" ,
68+ "fontweight" : " normal" ,
69+ "use_bits_from_map" : true ,
70+ "dump_json" : false ,
71+ "render_svg" : true
72+ }
73+ }
74+ },
75+ "title" : " Config" ,
76+ "type" : " object"
77+ },
78+ "corsair___generators__verilog__VerilogGenerator__Config" : {
79+ "additionalProperties" : false ,
80+ "description" : " Configuration for the Verilog generator." ,
81+ "properties" : {
82+ "kind" : {
83+ "const" : " verilog" ,
84+ "default" : " verilog" ,
85+ "description" : " Generator kind discriminator." ,
86+ "title" : " Kind" ,
87+ "type" : " string"
88+ },
89+ "reset_style" : {
90+ "$ref" : " #/$defs/ResetStyle" ,
91+ "default" : " async_neg"
92+ }
93+ },
94+ "title" : " Config" ,
95+ "type" : " object"
96+ },
97+ "corsair___generators__vhdl__VhdlGenerator__Config" : {
98+ "additionalProperties" : false ,
99+ "description" : " Configuration for the VHDL generator." ,
100+ "properties" : {
101+ "kind" : {
102+ "const" : " vhdl" ,
103+ "default" : " vhdl" ,
104+ "description" : " Generator kind discriminator." ,
105+ "title" : " Kind" ,
106+ "type" : " string"
107+ },
108+ "reset_style" : {
109+ "$ref" : " #/$defs/ResetStyle" ,
110+ "default" : " async_neg"
111+ }
112+ },
113+ "title" : " Config" ,
114+ "type" : " object"
115+ },
116+ "corsair___generators__wavedrom__WaveDromGenerator__Config" : {
117+ "additionalProperties" : false ,
118+ "description" : " Configuration for the WaveDrom generator." ,
119+ "properties" : {
120+ "kind" : {
121+ "const" : " wavedrom" ,
122+ "default" : " wavedrom" ,
123+ "description" : " Generator kind discriminator." ,
124+ "title" : " Kind" ,
125+ "type" : " string"
126+ },
127+ "vspace" : {
128+ "default" : 80 ,
129+ "description" : " Vertical space between lanes." ,
130+ "minimum" : 20 ,
131+ "title" : " Vspace" ,
132+ "type" : " integer"
133+ },
134+ "hspace" : {
135+ "default" : 800 ,
136+ "description" : " Horizontal space between lanes." ,
137+ "minimum" : 40 ,
138+ "title" : " Hspace" ,
139+ "type" : " integer"
140+ },
141+ "lanes" : {
142+ "default" : 1 ,
143+ "description" : " Number of lanes." ,
144+ "minimum" : 1 ,
145+ "title" : " Lanes" ,
146+ "type" : " integer"
147+ },
148+ "bits" : {
149+ "default" : 32 ,
150+ "description" : " Overall bit width." ,
151+ "minimum" : 4 ,
152+ "title" : " Bits" ,
153+ "type" : " integer"
154+ },
155+ "hflip" : {
156+ "default" : false ,
157+ "description" : " Horizontal flip." ,
158+ "title" : " Hflip" ,
159+ "type" : " boolean"
160+ },
161+ "vflip" : {
162+ "default" : false ,
163+ "description" : " Vertical flip." ,
164+ "title" : " Vflip" ,
165+ "type" : " boolean"
166+ },
167+ "fontsize" : {
168+ "default" : 14 ,
169+ "description" : " Font size." ,
170+ "minimum" : 6 ,
171+ "title" : " Fontsize" ,
172+ "type" : " integer"
173+ },
174+ "fontfamily" : {
175+ "default" : " sans-serif" ,
176+ "description" : " Font family." ,
177+ "title" : " Fontfamily" ,
178+ "type" : " string"
179+ },
180+ "fontweight" : {
181+ "default" : " normal" ,
182+ "description" : " Font weight." ,
183+ "title" : " Fontweight" ,
184+ "type" : " string"
185+ },
186+ "use_bits_from_map" : {
187+ "default" : true ,
188+ "description" : " Use the bit width from the register map. When True, `bits` is ignored." ,
189+ "title" : " Use Bits From Map" ,
190+ "type" : " boolean"
191+ },
192+ "dump_json" : {
193+ "default" : false ,
194+ "description" : " Dump the JSON wavedrom descriptions for every register." ,
195+ "title" : " Dump Json" ,
196+ "type" : " boolean"
197+ },
198+ "render_svg" : {
199+ "default" : true ,
200+ "description" : " Render the SVG images." ,
201+ "title" : " Render Svg" ,
202+ "type" : " boolean"
203+ }
204+ },
205+ "title" : " Config" ,
206+ "type" : " object"
207+ },
208+ "corsair___loaders__pymodule__PyModuleLoader__Config" : {
209+ "additionalProperties" : false ,
210+ "description" : " Configuration for the Python module loader." ,
211+ "properties" : {
212+ "mapfile" : {
213+ "default" : " csrmap.yaml" ,
214+ "description" : " Path to the register map file." ,
215+ "format" : " path" ,
216+ "title" : " Mapfile" ,
217+ "type" : " string"
218+ },
219+ "kind" : {
220+ "const" : " py" ,
221+ "default" : " py" ,
222+ "description" : " Loader kind discriminator." ,
223+ "title" : " Kind" ,
224+ "type" : " string"
225+ }
226+ },
227+ "title" : " Config" ,
228+ "type" : " object"
229+ },
230+ "corsair___loaders__serialized__SerializedLoader__Config" : {
231+ "additionalProperties" : false ,
232+ "description" : " Configuration for the serialized loader." ,
233+ "properties" : {
234+ "mapfile" : {
235+ "default" : " csrmap.yaml" ,
236+ "description" : " Path to the register map file." ,
237+ "format" : " path" ,
238+ "title" : " Mapfile" ,
239+ "type" : " string"
240+ },
241+ "kind" : {
242+ "description" : " Loader kind discriminator." ,
243+ "enum" : [
244+ " json" ,
245+ " yaml" ,
246+ " hjson"
247+ ],
248+ "title" : " Kind" ,
249+ "type" : " string"
250+ }
251+ },
252+ "required" : [
253+ " kind"
254+ ],
255+ "title" : " Config" ,
256+ "type" : " object"
257+ }
258+ },
259+ "additionalProperties" : false ,
260+ "description" : " Specification that describes how to build everything." ,
261+ "properties" : {
262+ "loader" : {
263+ "default" : {
264+ "mapfile" : " csrmap.yaml" ,
265+ "kind" : " yaml"
266+ },
267+ "description" : " Configuration for the loader." ,
268+ "discriminator" : {
269+ "mapping" : {
270+ "hjson" : " #/$defs/corsair___loaders__serialized__SerializedLoader__Config" ,
271+ "json" : " #/$defs/corsair___loaders__serialized__SerializedLoader__Config" ,
272+ "py" : " #/$defs/corsair___loaders__pymodule__PyModuleLoader__Config" ,
273+ "yaml" : " #/$defs/corsair___loaders__serialized__SerializedLoader__Config"
274+ },
275+ "propertyName" : " kind"
276+ },
277+ "oneOf" : [
278+ {
279+ "$ref" : " #/$defs/corsair___loaders__serialized__SerializedLoader__Config"
280+ },
281+ {
282+ "$ref" : " #/$defs/corsair___loaders__pymodule__PyModuleLoader__Config"
283+ }
284+ ],
285+ "title" : " Loader"
286+ },
287+ "generators" : {
288+ "additionalProperties" : {
289+ "discriminator" : {
290+ "mapping" : {
291+ "markdown" : " #/$defs/corsair___generators__markdown__MarkdownGenerator__Config" ,
292+ "verilog" : " #/$defs/corsair___generators__verilog__VerilogGenerator__Config" ,
293+ "vhdl" : " #/$defs/corsair___generators__vhdl__VhdlGenerator__Config" ,
294+ "wavedrom" : " #/$defs/corsair___generators__wavedrom__WaveDromGenerator__Config"
295+ },
296+ "propertyName" : " kind"
297+ },
298+ "oneOf" : [
299+ {
300+ "$ref" : " #/$defs/corsair___generators__verilog__VerilogGenerator__Config"
301+ },
302+ {
303+ "$ref" : " #/$defs/corsair___generators__vhdl__VhdlGenerator__Config"
304+ },
305+ {
306+ "$ref" : " #/$defs/corsair___generators__markdown__MarkdownGenerator__Config"
307+ },
308+ {
309+ "$ref" : " #/$defs/corsair___generators__wavedrom__WaveDromGenerator__Config"
310+ }
311+ ]
312+ },
313+ "description" : " Configuration for the generators to build all required files." ,
314+ "minProperties" : 1 ,
315+ "title" : " Generators" ,
316+ "type" : " object"
317+ }
318+ },
319+ "required" : [
320+ " generators"
321+ ],
322+ "title" : " BuildSpecification" ,
323+ "type" : " object"
324+ }
0 commit comments