[AArch64] Fix offset in FP-based epilogue restore for popless ret.

In a swiftcorocc function, on the restoreless epilogue path (using
llvm.ret.popless), we're using FP-based addressing to restore
callee-saved registers, as we can't rely on SP having been restored to
its initial value, since we're not restoring it at all.

FP-based CSR restore is novel and bound to find interesting divergence
from all of our existing epilogues.

In this case, at least the problem is pretty simple, and was even
visible in one of the original test case: we were missing the
statically-sized locals.  I haven't gotten to the point of convincing
myself this is sufficient yet, and I'm confident I'm missing some other
convoluted PEI-ism, but with this we can actually successfully run
a bunch of end-to-end swift tests!

While there, add an assert that checks that the FP/LR frame record
itself is only ever loaded from FP+0, without an offset.  If there's an
offset from FP, we must have goofed somewhere, since that breaks the
frame record linked list.

rdar://147838968

Author: ahmedbougacha

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

@@ -1578,7 +1578,7 @@ static MachineBasicBlock::iterator convertCalleeSaveRestoreToSPPrePostIncDec(
 }
 
 static void fixupCalleeSaveRestoreToFPBased(MachineInstr &MI,
-                                            uint64_t FPSPOffset) {
+                                            int64_t FPSPOffset) {
   assert(!AArch64InstrInfo::isSEHInstruction(MI));
 
   unsigned Opc = MI.getOpcode();
@@ -1615,7 +1615,13 @@ static void fixupCalleeSaveRestoreToFPBased(MachineInstr &MI,
   MachineOperand &OffsetOpnd = MI.getOperand(OffsetIdx);
   // All generated opcodes have scaled offsets.
   assert(FPSPOffset % Scale == 0);
-  OffsetOpnd.setImm(OffsetOpnd.getImm() - FPSPOffset / Scale);
+  int64_t ResidualOffset = OffsetOpnd.getImm() - (FPSPOffset / Scale);
+  OffsetOpnd.setImm(ResidualOffset);
+
+  assert((!MI.getOperand(0).isReg() ||
+          MI.getOperand(0).getReg() != AArch64::FP || ResidualOffset == 0) &&
+         "FP/LR frame record should be restored from FP+0");
+
 }
 
 // Fixup callee-save register save/restore instructions to take into account
@@ -2550,8 +2556,9 @@ void AArch64FrameLowering::emitEpilogue(MachineFunction &MF,
       fixupCalleeSaveRestoreStackOffset(*LastPopI, AFI->getLocalStackSize(),
                                         NeedsWinCFI, &HasWinCFI);
       // if FP-based addressing, rewrite CSR restores from SP to FP
-      fixupCalleeSaveRestoreToFPBased(
-          *LastPopI, AFI->getCalleeSaveBaseToFrameRecordOffset());
+      int64_t FPOffset = AFI->getCalleeSaveBaseToFrameRecordOffset() +
+                         AFI->getLocalStackSize();
+      fixupCalleeSaveRestoreToFPBased(*LastPopI, FPOffset);
     } else if (CombineSPBump)
       fixupCalleeSaveRestoreStackOffset(*LastPopI, AFI->getLocalStackSize(),
                                         NeedsWinCFI, &HasWinCFI);

llvm/test/CodeGen/AArch64/swiftcorocc-ret-popless.ll

@@ -42,8 +42,8 @@ define swiftcorocc i64 @test_intrin() #0 {
 ; CHECK-NEXT:    cbz x0, LBB1_2
 ; CHECK-NEXT:  ; %bb.1: ; %else
 ; CHECK-NEXT:    add x16, x29, #16
-; CHECK-NEXT:    ldp x26, x25, [x29] ; 16-byte Folded Reload
-; CHECK-NEXT:    ldp x29, x30, [x29, #16] ; 16-byte Folded Reload
+; CHECK-NEXT:    ldp x26, x25, [x29, #-16] ; 16-byte Folded Reload
+; CHECK-NEXT:    ldp x29, x30, [x29] ; 16-byte Folded Reload
 ; CHECK-NEXT:    autib x30, x16
 ; CHECK-NEXT:    ret
 ; CHECK-NEXT:  LBB1_2: ; %then