Merge branch 'crc_exclusion' into debug_1g_mac

Author: kavitha-etl

rtl/axis_gmii_rx.v

@@ -178,10 +178,14 @@ reg gmii_rx_er_d2 = 1'b0;
 reg gmii_rx_er_d3 = 1'b0;
 reg gmii_rx_er_d4 = 1'b0;
 
-reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}, m_axis_tdata_next;
-reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next;
-reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next;
-reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next;
+reg [DATA_WIDTH-1:0] m_axis_tdata_reg [4:0];
+reg [DATA_WIDTH-1:0] m_axis_tdata_next;
+reg [4:0] m_axis_tvalid_reg = 5'b0;
+reg m_axis_tvalid_next;
+reg [4:0] m_axis_tlast_reg = 5'b0;
+reg m_axis_tlast_next;
+reg [4:0] m_axis_tuser_reg = 5'b0;
+reg m_axis_tuser_next;
 
 reg start_packet_int_reg = 1'b0;
 reg start_packet_reg = 1'b0;
@@ -255,12 +259,72 @@ wire [31:0] crc_next;
 
 
 
+// debug out
+
+
+    assign state_reg_out = state_reg;
+    assign state_next_out = state_next;
+    assign reset_crc_out = reset_crc;
+    assign update_crc_out = update_crc;
+    
+    assign mii_odd_out = mii_odd ;
+    assign in_frame_out = in_frame;
+    
+    assign gmii_rxd_d0_out = gmii_rxd_d0;
+    assign gmii_rxd_d1_out = gmii_rxd_d1;
+    assign gmii_rxd_d2_out = gmii_rxd_d2;
+    assign gmii_rxd_d3_out = gmii_rxd_d3;
+    assign gmii_rxd_d4_out = gmii_rxd_d4;
+    
+    assign gmii_rx_dv_d0_out = gmii_rx_dv_d0;
+    assign gmii_rx_dv_d1_out = gmii_rx_dv_d1;
+    assign gmii_rx_dv_d2_out = gmii_rx_dv_d2;
+    assign gmii_rx_dv_d3_out = gmii_rx_dv_d3;
+    assign gmii_rx_dv_d4_out = gmii_rx_dv_d4;
+    
+    assign gmii_rx_er_d0_out = gmii_rx_er_d0;
+    assign gmii_rx_er_d1_out = gmii_rx_er_d1;
+    assign gmii_rx_er_d2_out = gmii_rx_er_d2;
+    assign gmii_rx_er_d3_out = gmii_rx_er_d3;
+    assign gmii_rx_er_d4_out= gmii_rx_er_d4;
+    
+    assign m_axis_tdata_reg_out = m_axis_tdata_reg;
+    assign m_axis_tdata_next_out = m_axis_tdata_next;
+    assign m_axis_tvalid_reg_out = m_axis_tvalid_reg;
+    assign m_axis_tvalid_next_out = m_axis_tvalid_next;
+    assign m_axis_tlast_reg_out = m_axis_tlast_reg; 
+    assign m_axis_tlast_next_out = m_axis_tlast_next;
+    assign m_axis_tuser_reg_out = m_axis_tuser_reg; 
+    assign m_axis_tuser_next_out = m_axis_tuser_next;
+    
+    assign start_packet_int_reg_out = start_packet_int_reg;
+    assign start_packet_reg_out = start_packet_reg;
+    assign error_bad_frame_reg_out = error_bad_frame_reg; 
+    assign error_bad_frame_next_out = error_bad_frame_next;
+    assign error_bad_fcs_reg_out = error_bad_fcs_reg;
+    assign error_bad_fcs_next_out = error_bad_fcs_next;
+    
+    assign ptp_ts_reg_out = ptp_ts_reg;
+    
+    assign crc_state_out = crc_state;
+    assign crc_next_out = crc_next;
+
+    assign clk_enable_out = clk_enable;
+    assign mii_select_out = rst;
+
+    /*
+     * Configuration
+     */
+    assign cfg_rx_enable_out = gmii_rx_dv;
+
+
+
 
 
-assign m_axis_tdata = m_axis_tdata_reg;
-assign m_axis_tvalid = m_axis_tvalid_reg;
-assign m_axis_tlast = m_axis_tlast_reg;
-assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, m_axis_tuser_reg} : m_axis_tuser_reg;
+assign m_axis_tdata = m_axis_tdata_reg[4];
+assign m_axis_tvalid = m_axis_tvalid_reg[4] & ~(|m_axis_tlast_reg[4:1]);
+assign m_axis_tlast = m_axis_tlast_reg[0];
+assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, m_axis_tuser_reg[4]} : m_axis_tuser_reg[4];
 
 assign start_packet = start_packet_reg;
 assign error_bad_frame = error_bad_frame_reg;
@@ -364,10 +428,10 @@ end
 always @(posedge clk) begin
     state_reg <= state_next;
 
-    m_axis_tdata_reg <= m_axis_tdata_next;
-    m_axis_tvalid_reg <= m_axis_tvalid_next;
-    m_axis_tlast_reg <= m_axis_tlast_next;
-    m_axis_tuser_reg <= m_axis_tuser_next;
+    m_axis_tdata_reg  <= {m_axis_tdata_reg[3:0],m_axis_tdata_next};
+    m_axis_tvalid_reg <= {m_axis_tvalid_reg[3:0],m_axis_tvalid_next};
+    m_axis_tlast_reg  <= {m_axis_tlast_reg[3:0],m_axis_tlast_next};
+    m_axis_tuser_reg  <= {m_axis_tuser_reg[3:0],m_axis_tuser_next};
 
     start_packet_int_reg <= 1'b0;
     start_packet_reg <= 1'b0;