delay value as parameter

Author: kavitha-etl

rtl/iddr.v

@@ -35,7 +35,9 @@ module iddr #
 (
     // Width of register in bits
     parameter WIDTH = 1,
-    parameter INSERT_BUFFERS = "FALSE"
+    parameter INSERT_BUFFERS = "FALSE",
+    // Can be count or time depending on delay type
+    parameter [8:0] DELAY_VALUE = 9'h19
 )
 (
     input  wire             clk,
@@ -127,7 +129,7 @@ end
         q_reg_1 <= d_reg_1;
         q_reg_2 <= d_reg_2;
     end
-    
+
     assign q1 = q_reg_1;
     assign q2 = q_reg_2;
 

rtl/rgmii_phy_if.v

@@ -45,7 +45,9 @@ module rgmii_phy_if #
     parameter CLOCK_INPUT_STYLE = "BUFIO",
     // Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
     parameter USE_CLK90 = "TRUE",
-    parameter INSERT_BUFFERS = "TRUE"
+    parameter INSERT_BUFFERS = "TRUE",
+    // Delay value for input data in count or time units
+    parameter [8:0] DELAY_VALUE = 9'h19
 )
 (
     // Reset, synchronous to gmii_gtx_clk
@@ -101,7 +103,8 @@ ssio_ddr_in #
     .TARGET(TARGET),
     .CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
     .WIDTH(5),
-    .INSERT_BUFFERS(INSERT_BUFFERS)
+    .INSERT_BUFFERS(INSERT_BUFFERS),
+    .DELAY_VALUE (DELAY_VALUE)
 )
 rx_ssio_ddr_inst (
     .input_clk(rgmii_rxc),

rtl/ssio_ddr_in.v

@@ -41,7 +41,8 @@ module ssio_ddr_in #
     parameter CLOCK_INPUT_STYLE = "BUFG",
     // Width of register in bits
     parameter WIDTH = 1,
-    parameter INSERT_BUFFERS = "FALSE"
+    parameter INSERT_BUFFERS = "FALSE",
+    parameter [8:0] DELAY_VALUE = 9'h19
 )
 (
     input  wire             input_clk,
@@ -145,7 +146,8 @@ endgenerate
 
 iddr #(
     .WIDTH(WIDTH),
-    .INSERT_BUFFERS(INSERT_BUFFERS)
+    .INSERT_BUFFERS(INSERT_BUFFERS),
+    .DELAY_VALUE(DELAY_VALUE)
 )
 data_iddr_inst (
     .clk(clk_io),