remove debug signals

Author: kavitha-etl

rtl/iddr.v

@@ -39,8 +39,6 @@ module iddr #
 )
 (
     input  wire             clk,
-    // idelay count output
-    output wire [(WIDTH*9)-1:0]      cnt_value_out,
     // Data input   
     input  wire [WIDTH-1:0] d,
 
@@ -81,7 +79,7 @@ end
 
 for (n = 0; n < WIDTH; n = n + 1) begin : iddr
     // Use IDELAYE3 for Ultrascale and Ultrascale+ devices to adjust delay between clock and data
-    // set delay format to count and delay value to 9'h19 (2 ns at 125 MHz approximate) 
+    // found delay count value by sweeping and checking the output
    IDELAYE3 #(
       .CASCADE("NONE"),          
       .DELAY_FORMAT("COUNT"),  // Units of the DELAY_VALUE (COUNT, TIME)  

rtl/rgmii_phy_if.v

@@ -87,10 +87,7 @@ module rgmii_phy_if #
      // 2'b10: 1G
      // 2'b01: 100M
      // 2'b00: 10M
-    input  wire [1:0]  speed,
-    output wire rx_gmii_clk,
-
-    output wire [(5*9)-1:0] cnt_value_out
+    input  wire [1:0]  speed
 );
 
 
@@ -100,9 +97,6 @@ wire clk;
 wire rgmii_rx_ctl_1;
 wire rgmii_rx_ctl_2;
 
-// for ila-debug
-assign rx_gmii_clk = gmii_rx_clk;
-
 ssio_ddr_in #
 (
     .TARGET(TARGET),
@@ -115,8 +109,7 @@ rx_ssio_ddr_inst (
     .input_d({rgmii_rd, rgmii_rx_ctl}),
     .output_clk(gmii_rx_clk),
     .output_q1({gmii_rxd[3:0], rgmii_rx_ctl_1}),
-    .output_q2({gmii_rxd[7:4], rgmii_rx_ctl_2}),
-    .cnt_value_out(cnt_value_out)
+    .output_q2({gmii_rxd[7:4], rgmii_rx_ctl_2})
 );
 
 assign gmii_rx_dv = rgmii_rx_ctl_1;

rtl/ssio_ddr_in.v

@@ -51,9 +51,7 @@ module ssio_ddr_in #
     output wire             output_clk,
 
     output wire [WIDTH-1:0] output_q1,
-    output wire [WIDTH-1:0] output_q2,
-    // idelay count output
-    output wire [(WIDTH*9)-1:0]      cnt_value_out
+    output wire [WIDTH-1:0] output_q2
 );
 
 wire input_clk_int;
@@ -153,9 +151,7 @@ data_iddr_inst (
     .clk(clk_io),
     .d(input_d),
     .q1(output_q1),
-    .q2(output_q2),
-    .cnt_value_out(cnt_value_out)
-
+    .q2(output_q2)
 );
 
 endmodule