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kavitha-etlkavitha-etl
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clean up and remove vio
1 parent e6cb0c6 commit 68cb8df

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3 files changed

+36
-130
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3 files changed

+36
-130
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‎rtl/iddr.v‎

Lines changed: 30 additions & 45 deletions
Original file line numberDiff line numberDiff line change
@@ -33,27 +33,15 @@ THE SOFTWARE.
3333
*/
3434
module iddr #
3535
(
36-
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
37-
parameter TARGET = "GENERIC",
38-
// IODDR style ("IODDR", "IODDR2")
39-
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
40-
// Use IODDR2 for Spartan-6
41-
parameter IODDR_STYLE = "IODDR2",
4236
// Width of register in bits
4337
parameter WIDTH = 1,
4438
parameter INSERT_BUFFERS = "FALSE"
4539
)
4640
(
4741
input wire clk,
48-
input wire rst,
49-
input wire en,
50-
input wire en_vtc,
51-
input wire inc,
52-
input wire load,
53-
input wire [8:0] cnt_value_in,
42+
// idelay count output
5443
output wire [(WIDTH*9)-1:0] cnt_value_out,
5544
// Data input
56-
5745
input wire [WIDTH-1:0] d,
5846

5947
output wire [WIDTH-1:0] q1,
@@ -75,11 +63,7 @@ Provides a consistent input DDR flip flop across multiple FPGA families
7563
*/
7664
wire [WIDTH-1:0] d_int;
7765
wire [WIDTH-1:0] delayed_data_int;
78-
reg en_ff,en_ff1;
79-
always @(posedge clk) begin
80-
en_ff <= en;
81-
en_ff1 <= en_ff;
82-
end
66+
8367
genvar n;
8468

8569
generate
@@ -96,34 +80,35 @@ end else begin
9680
end
9781

9882
for (n = 0; n < WIDTH; n = n + 1) begin : iddr
99-
83+
// Use IDELAYE3 for Ultrascale and Ultrascale+ devices to adjust delay between clock and data
84+
// set delay format to count and delay value to 9'h19 (2 ns at 125 MHz approximate)
10085
IDELAYE3 #(
101-
.CASCADE("NONE"), // Cascade setting (MASTER, NONE, SLAVE_END, SLAVE_MIDDLE)
102-
.DELAY_FORMAT("COUNT"), // Units of the DELAY_VALUE (COUNT, TIME)
103-
.DELAY_SRC("IDATAIN"), // Delay input (DATAIN, IDATAIN)
104-
.DELAY_TYPE("VARIABLE"), // Set the type of tap delay line (FIXED, VARIABLE, VAR_LOAD)
105-
.DELAY_VALUE(9'h19), // Input delay value setting
106-
.IS_CLK_INVERTED(1'b0), // Optional inversion for CLK
107-
.IS_RST_INVERTED(1'b0), // Optional inversion for RST
108-
.REFCLK_FREQUENCY(300.0), // IDELAYCTRL clock input frequency in MHz (200.0-800.0)
109-
.SIM_DEVICE("ULTRASCALE_PLUS"), // Set the device version for simulation functionality (ULTRASCALE)
110-
.UPDATE_MODE("ASYNC") // Determines when updates to the delay will take effect (ASYNC, MANUAL, SYNC)
86+
.CASCADE("NONE"),
87+
.DELAY_FORMAT("COUNT"), // Units of the DELAY_VALUE (COUNT, TIME)
88+
.DELAY_SRC("IDATAIN"),
89+
.DELAY_TYPE("FIXED"),
90+
.DELAY_VALUE(9'h19),
91+
.IS_CLK_INVERTED(1'b0),
92+
.IS_RST_INVERTED(1'b0),
93+
.REFCLK_FREQUENCY(300.0),
94+
.SIM_DEVICE("ULTRASCALE_PLUS"),
95+
.UPDATE_MODE("ASYNC")
11196
)
11297
IDELAYE3_inst (
113-
.CASC_OUT(), // 1-bit output: Cascade delay output to ODELAY input cascade
114-
.CNTVALUEOUT(cnt_value_out[(n*9)+8 : n*9 ]), // 9-bit output: Counter value output
115-
.DATAOUT(delayed_data_int[n]), // 1-bit output: Delayed data output
116-
.CASC_IN(0), // 1-bit input: Cascade delay input from slave ODELAY CASCADE_OUT
117-
.CASC_RETURN(0), // 1-bit input: Cascade delay returning from slave ODELAY DATAOUT
118-
.CE(en_ff & ~en_ff1), // 1-bit input: Active-High enable increment/decrement input
119-
.CLK(clk), // 1-bit input: Clock input
120-
.CNTVALUEIN(cnt_value_in), // 9-bit input: Counter value input
121-
.DATAIN(0), // 1-bit input: Data input from the logic
122-
.EN_VTC(en_vtc), // 1-bit input: Keep delay constant over VT
123-
.IDATAIN(d_int[n]), // 1-bit input: Data input from the IOBUF
124-
.INC(inc), // 1-bit input: Increment / Decrement tap delay input
125-
.LOAD(load), // 1-bit input: Load DELAY_VALUE input
126-
.RST(rst) // 1-bit input: Asynchronous Reset to the DELAY_VALUE
98+
.CASC_OUT(),
99+
.CNTVALUEOUT(cnt_value_out[(n*9)+8 : n*9 ]),
100+
.DATAOUT(delayed_data_int[n]),
101+
.CASC_IN(0),
102+
.CASC_RETURN(0),
103+
.CE(0),
104+
.CLK(clk),
105+
.CNTVALUEIN(0),
106+
.DATAIN(0),
107+
.EN_VTC(0),
108+
.IDATAIN(d_int[n]),
109+
.INC(0),
110+
.LOAD(0),
111+
.RST(0)
127112
);
128113

129114
end
@@ -133,11 +118,11 @@ end
133118
reg [WIDTH-1:0] q_reg_1 = {WIDTH{1'b0}};
134119
reg [WIDTH-1:0] q_reg_2 = {WIDTH{1'b0}};
135120

136-
always @(negedge clk) begin
121+
always @(posedge clk) begin
137122
d_reg_1 <= delayed_data_int;
138123
end
139124

140-
always @(posedge clk) begin
125+
always @(negedge clk) begin
141126
d_reg_2 <= delayed_data_int;
142127
end
143128

‎rtl/rgmii_phy_if.v‎

Lines changed: 5 additions & 66 deletions
Original file line numberDiff line numberDiff line change
@@ -88,79 +88,25 @@ module rgmii_phy_if #
8888
// 2'b01: 100M
8989
// 2'b00: 10M
9090
input wire [1:0] speed,
91-
output wire [47:0] debug_rgmii,
92-
output wire rx_rgmii_clk,
9391
output wire rx_gmii_clk,
9492

95-
input wire rst_idelay,
96-
input wire en,
97-
input wire en_vtc,
98-
input wire inc,
99-
input wire load,
100-
input wire [8:0] cnt_value_in,
10193
output wire [(5*9)-1:0] cnt_value_out
10294
);
103-
// Debug _signal
104-
wire rgmii_rxc_debug;
105-
wire [3:0] rgmii_rd_debug;
106-
wire rgmii_rx_ctl_debug;
107-
wire rgmii_txc_debug;
108-
wire [3:0] rgmii_td_debug;
109-
wire rgmii_tx_ctl_debug;
110-
111-
wire gmii_rx_clk_debug;
112-
wire [7:0] gmii_rxd_debug;
113-
wire gmii_rx_dv_debug;
114-
wire gmii_rx_er_debug;
115-
116-
wire gmii_gtx_clk_debug;
117-
wire [7:0] gmii_txd_debug;
118-
wire gmii_tx_en_debug;
119-
wire gmii_tx_er_debug;
120-
assign rgmii_rxc_debug = 0;
121-
assign rgmii_rd_debug = 0;
122-
assign rgmii_rx_ctl_debug = 0;
123-
assign rgmii_txc_debug = 0;
124-
assign rgmii_td_debug = 0;
125-
assign rgmii_tx_ctl_debug = 0;
126-
127-
assign gmii_rx_clk_debug = gmii_rx_clk;
128-
assign gmii_rxd_debug = gmii_rxd;
129-
assign gmii_rx_dv_debug= gmii_rx_dv;
130-
assign gmii_rx_er_debug= gmii_rx_er;
131-
132-
assign gmii_gtx_clk_debug= gmii_gtx_clk;
133-
assign gmii_txd_debug= gmii_txd;
134-
assign gmii_tx_en_debug= gmii_tx_en;
135-
assign gmii_tx_er_debug= gmii_tx_er;
136-
assign debug_rgmii = {rgmii_rxc_debug,
137-
rgmii_rd_debug,
138-
rgmii_rx_ctl_debug,
139-
rgmii_txc_debug,
140-
rgmii_td_debug,
141-
rgmii_tx_ctl_debug,
142-
gmii_rx_clk_debug,
143-
gmii_rxd_debug,
144-
gmii_rx_dv_debug,
145-
gmii_rx_er_debug,
146-
gmii_gtx_clk_debug,
147-
gmii_txd_debug,
148-
gmii_tx_en_debug,
149-
gmii_tx_er_debug};
150-
assign rx_gmii_clk = gmii_rx_clk_debug;
151-
assign rx_rgmii_clk = rgmii_rxc_debug;
95+
96+
15297
wire clk;
15398

15499
// receive
155-
156100
wire rgmii_rx_ctl_1;
157101
wire rgmii_rx_ctl_2;
158102

103+
// for ila-debug
104+
assign rx_gmii_clk = gmii_rx_clk;
105+
159106
ssio_ddr_in #
160107
(
161108
.TARGET(TARGET),
162109
.CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
163-
.IODDR_STYLE(IODDR_STYLE),
164110
.WIDTH(5),
165111
.INSERT_BUFFERS(INSERT_BUFFERS)
166112
)
@@ -170,14 +116,7 @@ rx_ssio_ddr_inst (
170116
.output_clk(gmii_rx_clk),
171117
.output_q1({gmii_rxd[3:0], rgmii_rx_ctl_1}),
172118
.output_q2({gmii_rxd[7:4], rgmii_rx_ctl_2}),
173-
.rst(rst_idelay),
174-
.en(en),
175-
.en_vtc(en_vtc),
176-
.inc(inc),
177-
.load(load),
178-
.cnt_value_in(cnt_value_in),
179119
.cnt_value_out(cnt_value_out)
180-
// Data input
181120
);
182121

183122
assign gmii_rx_dv = rgmii_rx_ctl_1;

‎rtl/ssio_ddr_in.v‎

Lines changed: 1 addition & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -35,10 +35,6 @@ module ssio_ddr_in #
3535
(
3636
// target ("SIM", "GENERIC", "XILINX", "ALTERA")
3737
parameter TARGET = "GENERIC",
38-
// IODDR style ("IODDR", "IODDR2")
39-
// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
40-
// Use IODDR2 for Spartan-6
41-
parameter IODDR_STYLE = "IODDR2",
4238
// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
4339
// Use BUFR for Virtex-6, 7-series
4440
// Use BUFG for Virtex-5, Spartan-6, Ultrascale
@@ -56,13 +52,7 @@ module ssio_ddr_in #
5652

5753
output wire [WIDTH-1:0] output_q1,
5854
output wire [WIDTH-1:0] output_q2,
59-
60-
input wire rst,
61-
input wire en,
62-
input wire en_vtc,
63-
input wire inc,
64-
input wire load,
65-
input wire [8:0] cnt_value_in,
55+
// idelay count output
6656
output wire [(WIDTH*9)-1:0] cnt_value_out
6757
);
6858

@@ -156,8 +146,6 @@ endgenerate
156146

157147

158148
iddr #(
159-
.TARGET(TARGET),
160-
.IODDR_STYLE(IODDR_STYLE),
161149
.WIDTH(WIDTH),
162150
.INSERT_BUFFERS(INSERT_BUFFERS)
163151
)
@@ -166,12 +154,6 @@ data_iddr_inst (
166154
.d(input_d),
167155
.q1(output_q1),
168156
.q2(output_q2),
169-
.rst(rst),
170-
.en(en),
171-
.en_vtc(en_vtc),
172-
.inc(inc),
173-
.load(load),
174-
.cnt_value_in(cnt_value_in),
175157
.cnt_value_out(cnt_value_out)
176158

177159
);

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