signal type

Author: kavitha-etl

rtl/axis_gmii_tx.v

@@ -92,7 +92,7 @@ module axis_gmii_tx #
 
     // Debug ports
 
-    output clk_out,
+    output wire clk_out,
     output wire [DATA_WIDTH-1:0]      tdata_out,
     output  wire                      talid_out,
     output  wire                      last_out,

rtl/eth_mac_1g.v

@@ -195,7 +195,7 @@ module eth_mac_1g #
     input  wire                         cfg_rx_pfc_en,
 
     // debug
-    output clk_out,
+    output wire clk_out,
     output wire [DATA_WIDTH-1:0]      tdata_out,
     output  wire                      talid_out,
     output  wire                      last_out,
@@ -204,7 +204,7 @@ module eth_mac_1g #
     output  wire                      cfg_tx_enable_out,
     output wire                       start_packet_out,
     output wire                       error_underflow_out,
-    output [2:0]                      state_reg_out,
+    output wire [2:0]                      state_reg_out,
 
     output wire [DATA_WIDTH-1:0]     gmii_txd_out,
     output wire                      gmii_tx_en_out,