Add bus interface pragmas to rgmii_phy_if

Author: ollie-etl

rtl/eth_mac_1g_rgmii.v

@@ -189,32 +189,33 @@ rgmii_phy_if #(
     .USE_CLK90(USE_CLK90)
 )
 rgmii_phy_if_inst (
-    .clk(gtx_clk),
-    .clk90(gtx_clk90),
+    .mac_gmii_gtx_clk(gtx_clk),
+    .mac_gmii_gtx_clk_90(gtx_clk90),
     .rst(gtx_rst),
 
     .mac_gmii_rx_clk(rx_clk),
     .mac_gmii_rx_rst(rx_rst),
     .mac_gmii_rxd(mac_gmii_rxd),
     .mac_gmii_rx_dv(mac_gmii_rx_dv),
     .mac_gmii_rx_er(mac_gmii_rx_er),
-    .mac_gmii_tx_clk(tx_clk),
     .mac_gmii_tx_rst(tx_rst),
     .mac_gmii_tx_clk_en(mac_gmii_tx_clk_en),
     .mac_gmii_txd(mac_gmii_txd),
     .mac_gmii_tx_en(mac_gmii_tx_en),
     .mac_gmii_tx_er(mac_gmii_tx_er),
 
-    .phy_rgmii_rx_clk(rgmii_rx_clk),
-    .phy_rgmii_rxd(rgmii_rxd),
+    .phy_rgmii_rxc(rgmii_rx_clk),
+    .phy_rgmii_rd(rgmii_rxd),
     .phy_rgmii_rx_ctl(rgmii_rx_ctl),
-    .phy_rgmii_tx_clk(rgmii_tx_clk),
-    .phy_rgmii_txd(rgmii_txd),
+    .phy_rgmii_txc(rgmii_tx_clk),
+    .phy_rgmii_td(rgmii_txd),
     .phy_rgmii_tx_ctl(rgmii_tx_ctl),
 
     .speed(speed)
 );
 
+assign tx_clk = gtx_clk;
+
 eth_mac_1g #(
     .ENABLE_PADDING(ENABLE_PADDING),
     .MIN_FRAME_LENGTH(MIN_FRAME_LENGTH)

rtl/rgmii_phy_if.v

@@ -47,24 +47,27 @@ module rgmii_phy_if #
     parameter USE_CLK90 = "TRUE"
 )
 (
-    input  wire        clk,
-    input  wire        clk90,
+    // Reset, synchronous to mac_gmii_gtx_clk
     input  wire        rst,
 
     /*
      * GMII interface to MAC
      */
-    output wire        mac_gmii_rx_clk,
+    (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME mac_gmii, CAN_DEBUG false" *)
+    (* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii RX_CLK" *)  output wire        mac_gmii_rx_clk,
+    (* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii RXD" *)     output wire [7:0]  mac_gmii_rxd,
+    (* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii RX_DV" *)   output wire        mac_gmii_rx_dv,
+    (* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii RX_ER" *)   output wire        mac_gmii_rx_er,
+
+    (* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii GTX_CLK" *) input wire         mac_gmii_gtx_clk,
+    (* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii TXD" *)     input  wire [7:0]  mac_gmii_txd,
+    (* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii TX_EN" *)   input  wire        mac_gmii_tx_en,
+    (* X_INTERFACE_INFO = "xilinx.com:interface:gmii_rtl:1.0 mac_gmii TX_ER" *)   input  wire        mac_gmii_tx_er,
+    // These are non-standard gmii signals to control the MAC
+    input  wire        mac_gmii_gtx_clk_90,
     output wire        mac_gmii_rx_rst,
-    output wire [7:0]  mac_gmii_rxd,
-    output wire        mac_gmii_rx_dv,
-    output wire        mac_gmii_rx_er,
-    output wire        mac_gmii_tx_clk,
     output wire        mac_gmii_tx_rst,
     output wire        mac_gmii_tx_clk_en,
-    input  wire [7:0]  mac_gmii_txd,
-    input  wire        mac_gmii_tx_en,
-    input  wire        mac_gmii_tx_er,
 
     /*
      * RGMII interface to PHY
@@ -80,9 +83,14 @@ module rgmii_phy_if #
     /*
      * Control
      */
+     // 2'b10: 1G
+     // 2'b01: 100M
+     // 2'b00: 10M
     input  wire [1:0]  speed
 );
 
+wire clk;
+
 // receive
 
 wire rgmii_rx_ctl_1;
@@ -204,7 +212,7 @@ oddr #(
     .WIDTH(1)
 )
 clk_oddr_inst (
-    .clk(USE_CLK90 == "TRUE" ? clk90 : clk),
+    .clk(USE_CLK90 == "TRUE" ? mac_gmii_gtx_clk_90 : clk),
     .d1(rgmii_tx_clk_1),
     .d2(rgmii_tx_clk_2),
     .q(phy_rgmii_txc)
@@ -222,15 +230,15 @@ data_oddr_inst (
     .q({phy_rgmii_td, phy_rgmii_tx_ctl})
 );
 
-assign mac_gmii_tx_clk = clk;
+assign clk = mac_gmii_gtx_clk;
 
 assign mac_gmii_tx_clk_en = gmii_clk_en;
 
 // reset sync
 reg [3:0] tx_rst_reg = 4'hf;
 assign mac_gmii_tx_rst = tx_rst_reg[0];
 
-always @(posedge mac_gmii_tx_clk or posedge rst) begin
+always @(posedge clk or posedge rst) begin
     if (rst) begin
         tx_rst_reg <= 4'hf;
     end else begin