@@ -208,7 +208,55 @@ module eth_mac_1g #
208208
209209 output wire [DATA_WIDTH- 1 :0 ] gmii_txd_out,
210210 output wire gmii_tx_en_out,
211- output wire gmii_tx_er_out
211+ output wire gmii_tx_er_out,
212+
213+ // debug rx
214+
215+ output wire [2 :0 ] state_reg_out,
216+ output wire [2 :0 ] state_next_out,
217+ output wire reset_crc_out,
218+ output wire update_crc_out,
219+ output wire mii_odd_out,
220+ output wire in_frame_out,
221+
222+ output wire [DATA_WIDTH- 1 :0 ] gmii_rxd_d0_out,
223+ output wire [DATA_WIDTH- 1 :0 ] gmii_rxd_d1_out,
224+ output wire [DATA_WIDTH- 1 :0 ] gmii_rxd_d2_out,
225+ output wire [DATA_WIDTH- 1 :0 ] gmii_rxd_d3_out,
226+ output wire [DATA_WIDTH- 1 :0 ] gmii_rxd_d4_out,
227+
228+ output wire gmii_rx_dv_d0_out,
229+ output wire gmii_rx_dv_d1_out,
230+ output wire gmii_rx_dv_d2_out,
231+ output wire gmii_rx_dv_d3_out,
232+ output wire gmii_rx_dv_d4_out,
233+
234+ output wire gmii_rx_er_d0_out,
235+ output wire gmii_rx_er_d1_out,
236+ output wire gmii_rx_er_d2_out,
237+ output wire gmii_rx_er_d3_out,
238+ output wire gmii_rx_er_d4_out,
239+
240+ output wire [DATA_WIDTH- 1 :0 ] m_axis_tdata_reg_out,
241+ output wire [DATA_WIDTH- 1 :0 ] m_axis_tdata_next_out,
242+ output wire m_axis_tvalid_reg_out,
243+ output wire m_axis_tvalid_next_out,
244+ output wire m_axis_tlast_reg_out,
245+ output wire m_axis_tlast_next_out,
246+ output wire m_axis_tuser_reg_out,
247+ output wire m_axis_tuser_next_out,
248+
249+ output wire start_packet_int_reg_out,
250+ output wire start_packet_reg_out,
251+ output wire error_bad_frame_reg_out,
252+ output wire error_bad_frame_next_out,
253+ output wire error_bad_fcs_reg_out,
254+ output wire error_bad_fcs_next_out,
255+
256+ output wire [PTP_TS_WIDTH- 1 :0 ] ptp_ts_reg_out,
257+
258+ output wire [31 :0 ] crc_state_out,
259+ output wire [31 :0 ] crc_next_out
212260);
213261
214262localparam MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE;
@@ -250,7 +298,52 @@ axis_gmii_rx_inst (
250298 .cfg_rx_enable(cfg_rx_enable),
251299 .start_packet(rx_start_packet),
252300 .error_bad_frame(rx_error_bad_frame),
253- .error_bad_fcs(rx_error_bad_fcs)
301+ .error_bad_fcs(rx_error_bad_fcs),
302+ .state_reg_out(state_reg_out),
303+ .state_next_out(state_next_out),
304+ .reset_crc_out(reset_crc_out),
305+ .update_crc_out(update_crc_out),
306+ .mii_odd_out(mii_odd_out),
307+ .in_frame_out(in_frame_out),
308+
309+ .gmii_rxd_d0_out(gmii_rxd_d0_out),
310+ .gmii_rxd_d1_out(gmii_rxd_d1_out),
311+ .gmii_rxd_d2_out(gmii_rxd_d2_out),
312+ .gmii_rxd_d3_out(gmii_rxd_d3_out),
313+ .gmii_rxd_d4_out(gmii_rxd_d4_out),
314+
315+ .gmii_rx_dv_d0_out(gmii_rx_dv_d0_out),
316+ .gmii_rx_dv_d1_out(gmii_rx_dv_d1_out),
317+ .gmii_rx_dv_d2_out(gmii_rx_dv_d2_out),
318+ .gmii_rx_dv_d3_out(gmii_rx_dv_d3_out),
319+ .gmii_rx_dv_d4_out(gmii_rx_dv_d4_out),
320+
321+ .gmii_rx_er_d0_out(gmii_rx_er_d0_out),
322+ .gmii_rx_er_d1_out(gmii_rx_er_d1_out),
323+ .gmii_rx_er_d2_out(gmii_rx_er_d2_out),
324+ .gmii_rx_er_d3_out(gmii_rx_er_d3_out),
325+ .gmii_rx_er_d4_out(gmii_rx_er_d4_out),
326+
327+ .m_axis_tdata_reg_out(m_axis_tdata_reg_out),
328+ .m_axis_tdata_next_out(m_axis_tdata_next_out),
329+ .m_axis_tvalid_reg_out( m_axis_tvalid_reg_out),
330+ .m_axis_tvalid_next_out( m_axis_tvalid_next_out),
331+ .m_axis_tlast_reg_out( m_axis_tlast_reg_out),
332+ .m_axis_tlast_next_out( m_axis_tlast_next_out),
333+ .m_axis_tuser_reg_out( m_axis_tuser_reg_out),
334+ .m_axis_tuser_next_out( m_axis_tuser_next_out),
335+
336+ .start_packet_int_reg_out(start_packet_int_reg_out),
337+ .start_packet_reg_out(start_packet_reg_out),
338+ .error_bad_frame_reg_out(error_bad_frame_reg_out),
339+ .error_bad_frame_next_out(error_bad_frame_next_out),
340+ .error_bad_fcs_reg_out(error_bad_fcs_reg_out),
341+ .error_bad_fcs_next_out(error_bad_fcs_next_out),
342+
343+ .ptp_ts_reg_out(ptp_ts_reg_out),
344+
345+ .crc_state_out(crc_state_out),
346+ .crc_next_out(crc_next_out)
254347);
255348
256349axis_gmii_tx #(
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