remove idelay control

Author: kavitha-etl

rtl/iddr.v

@@ -52,8 +52,6 @@ module iddr #
     input  wire             load,
     input  wire [8:0]      cnt_value_in,
     output wire [(WIDTH*9)-1:0]      cnt_value_out,
-    input  wire refclk,
-    output wire             rdy_idelay,
     // Data input   
 
     input  wire [WIDTH-1:0] d,
@@ -97,16 +95,6 @@ end else begin
     assign d_int = d;
 end
 
-IDELAYCTRL #(
-    .SIM_DEVICE("ULTRASCALE")  // Set the device version for simulation functionality (ULTRASCALE)
-)
-IDELAYCTRL_rx_inst (
-    .RDY(rdy_idelay),       // 1-bit output: Ready output
-    .REFCLK(refclk), // 1-bit input: Reference clock input
-    .RST(rst)        // 1-bit input: Active-High reset input. Asynchronous assert, synchronous deassert to
-                       // REFCLK.
-);
-
 for (n = 0; n < WIDTH; n = n + 1) begin : iddr
 
    IDELAYE3 #(

rtl/rgmii_phy_if.v

@@ -98,9 +98,7 @@ module rgmii_phy_if #
     input  wire             inc,
     input  wire             load,
     input  wire [8:0]       cnt_value_in,
-    output wire [(5*9)-1:0] cnt_value_out,
-    input  wire             refclk,
-    output wire             rdy_idelay
+    output wire [(5*9)-1:0] cnt_value_out
 );
     // Debug _signal
     wire rgmii_rxc_debug;
@@ -178,9 +176,7 @@ rx_ssio_ddr_inst (
     .inc(inc),
     .load(load),
     .cnt_value_in(cnt_value_in),
-    .cnt_value_out(cnt_value_out),
-    .refclk(refclk),
-    .rdy_idelay(rdy_idelay)
+    .cnt_value_out(cnt_value_out)
     // Data input   
 );
 

rtl/ssio_ddr_in.v

@@ -63,9 +63,7 @@ module ssio_ddr_in #
     input  wire             inc,
     input  wire             load,
     input  wire [8:0]      cnt_value_in,
-    output wire [(WIDTH*9)-1:0]      cnt_value_out,
-    input  wire             refclk,
-    output wire             rdy_idelay
+    output wire [(WIDTH*9)-1:0]      cnt_value_out
 );
 
 wire input_clk_int;
@@ -174,9 +172,7 @@ data_iddr_inst (
     .inc(inc),
     .load(load),
     .cnt_value_in(cnt_value_in),
-    .cnt_value_out(cnt_value_out),
-    .refclk(refclk),
-    .rdy_idelay(rdy_idelay)
+    .cnt_value_out(cnt_value_out)
 
 );