Update to compile (#1)

ollie-etl · web-flow · commit d6fa52a37d68 · 2025-01-03T15:15:20.000Z
diff --git a/rtl/arp_eth_rx.v b/rtl/arp_eth_rx.v
@@ -86,15 +86,15 @@ module arp_eth_rx #
     output wire                   error_invalid_header
 );
 
-parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
+localparam BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
 
-parameter HDR_SIZE = 28;
+localparam HDR_SIZE = 28;
 
-parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
+localparam CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
 
-parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
+localparam PTR_WIDTH = $clog2(CYCLE_COUNT);
 
-parameter OFFSET = HDR_SIZE % BYTE_LANES;
+localparam OFFSET = HDR_SIZE % BYTE_LANES;
 
 // bus width assertions
 initial begin
diff --git a/rtl/arp_eth_tx.v b/rtl/arp_eth_tx.v
@@ -82,15 +82,15 @@ module arp_eth_tx #
     output wire                   busy
 );
 
-parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
+localparam BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
 
-parameter HDR_SIZE = 28;
+localparam HDR_SIZE = 28;
 
-parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
+localparam CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
 
-parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
+localparam PTR_WIDTH = $clog2(CYCLE_COUNT);
 
-parameter OFFSET = HDR_SIZE % BYTE_LANES;
+localparam OFFSET = HDR_SIZE % BYTE_LANES;
 
 // bus width assertions
 initial begin
diff --git a/rtl/axis_baser_rx_64.v b/rtl/axis_baser_rx_64.v
@@ -406,7 +406,7 @@ always @(posedge clk) begin
         ptp_ts_adj_reg[15:0] <= ptp_ts_reg[15:0];
         {ptp_ts_borrow_reg, ptp_ts_adj_reg[45:16]} <= $signed({1'b0, ptp_ts_reg[45:16]}) - $signed(31'd1000000000);
         ptp_ts_adj_reg[47:46] <= 0;
-        ptp_ts_adj_reg[95:48] <= ptp_ts_reg[95:48] + 1;
+        ptp_ts_adj_reg[PTP_TS_WIDTH-1:48] <= ptp_ts_reg[PTP_TS_WIDTH-1:48] + 1;
     end
 
     if (encoded_rx_hdr == SYNC_CTRL && encoded_rx_data[7:0] == BLOCK_TYPE_START_0) begin
@@ -507,8 +507,8 @@ always @(posedge clk) begin
     if (delay_type == INPUT_TYPE_START_0 && delay_type_valid) begin
         start_packet_reg <= 2'b10;
         if (PTP_TS_FMT_TOD) begin
+            ptp_ts_reg <= ptp_ts;
             ptp_ts_reg[45:0] <= ptp_ts[45:0] + (ts_inc_reg >> 1);
-            ptp_ts_reg[95:48] <= ptp_ts[95:48];
         end else begin
             ptp_ts_reg <= ptp_ts + (ts_inc_reg >> 1);
         end
diff --git a/rtl/axis_baser_tx_64.v b/rtl/axis_baser_tx_64.v
@@ -88,8 +88,8 @@ module axis_baser_tx_64 #
     output wire                      error_underflow
 );
 
-parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH);
-parameter MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-KEEP_WIDTH+1);
+localparam EMPTY_WIDTH = $clog2(KEEP_WIDTH);
+localparam MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-KEEP_WIDTH+1);
 
 // bus width assertions
 initial begin
diff --git a/rtl/axis_gmii_tx.v b/rtl/axis_gmii_tx.v
@@ -90,7 +90,7 @@ module axis_gmii_tx #
     output wire                      error_underflow
 );
 
-parameter MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-1+1);
+localparam MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-1+1);
 
 // bus width assertions
 initial begin
diff --git a/rtl/axis_xgmii_tx_32.v b/rtl/axis_xgmii_tx_32.v
@@ -87,8 +87,8 @@ module axis_xgmii_tx_32 #
     output wire                      error_underflow
 );
 
-parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH);
-parameter MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-CTRL_WIDTH+1);
+localparam EMPTY_WIDTH = $clog2(KEEP_WIDTH);
+localparam MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-CTRL_WIDTH+1);
 
 // bus width assertions
 initial begin
diff --git a/rtl/axis_xgmii_tx_64.v b/rtl/axis_xgmii_tx_64.v
@@ -88,8 +88,8 @@ module axis_xgmii_tx_64 #
     output wire                      error_underflow
 );
 
-parameter EMPTY_WIDTH = $clog2(KEEP_WIDTH);
-parameter MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-CTRL_WIDTH+1);
+localparam EMPTY_WIDTH = $clog2(KEEP_WIDTH);
+localparam MIN_LEN_WIDTH = $clog2(MIN_FRAME_LENGTH-4-CTRL_WIDTH+1);
 
 // bus width assertions
 initial begin
@@ -171,7 +171,7 @@ reg [4+16-1:0] ts_inc_reg = 0;
 reg [DATA_WIDTH-1:0] xgmii_txd_reg = {CTRL_WIDTH{XGMII_IDLE}}, xgmii_txd_next;
 reg [CTRL_WIDTH-1:0] xgmii_txc_reg = {CTRL_WIDTH{1'b1}}, xgmii_txc_next;
 
-reg start_packet_reg = 2'b00;
+reg [1:0] start_packet_reg = 2'b00;
 reg error_underflow_reg = 1'b0, error_underflow_next;
 
 assign s_axis_tready = s_axis_tready_reg;
diff --git a/rtl/eth_arb_mux.v b/rtl/eth_arb_mux.v
@@ -87,7 +87,7 @@ module eth_arb_mux #
     output wire [USER_WIDTH-1:0]         m_eth_payload_axis_tuser
 );
 
-parameter CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_S_COUNT = $clog2(S_COUNT);
 
 reg frame_reg = 1'b0, frame_next;
 
diff --git a/rtl/eth_axis_rx.v b/rtl/eth_axis_rx.v
@@ -77,15 +77,15 @@ module eth_axis_rx #
     output wire                  error_header_early_termination
 );
 
-parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
+localparam BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
 
-parameter HDR_SIZE = 14;
+localparam HDR_SIZE = 14;
 
-parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
+localparam CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
 
-parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
+localparam PTR_WIDTH = $clog2(CYCLE_COUNT);
 
-parameter OFFSET = HDR_SIZE % BYTE_LANES;
+localparam OFFSET = HDR_SIZE % BYTE_LANES;
 
 // bus width assertions
 initial begin
diff --git a/rtl/eth_axis_tx.v b/rtl/eth_axis_tx.v
@@ -76,15 +76,15 @@ module eth_axis_tx #
     output wire                  busy
 );
 
-parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
+localparam BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
 
-parameter HDR_SIZE = 14;
+localparam HDR_SIZE = 14;
 
-parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
+localparam CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
 
-parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
+localparam PTR_WIDTH = $clog2(CYCLE_COUNT);
 
-parameter OFFSET = HDR_SIZE % BYTE_LANES;
+localparam OFFSET = HDR_SIZE % BYTE_LANES;
 
 // bus width assertions
 initial begin
diff --git a/rtl/eth_demux.v b/rtl/eth_demux.v
@@ -90,7 +90,7 @@ module eth_demux #
     input  wire [$clog2(M_COUNT)-1:0]    select
 );
 
-parameter CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
 
 reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
 reg drop_reg = 1'b0, drop_ctl, drop_next;
diff --git a/rtl/eth_mac_10g.v b/rtl/eth_mac_10g.v
@@ -183,8 +183,8 @@ module eth_mac_10g #
     input  wire                         cfg_rx_pfc_en
 );
 
-parameter MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE;
-parameter TX_USER_WIDTH_INT = MAC_CTRL_ENABLE ? (PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1 : 0) + 1 : TX_USER_WIDTH;
+localparam MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE;
+localparam TX_USER_WIDTH_INT = MAC_CTRL_ENABLE ? (PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1 : 0) + 1 : TX_USER_WIDTH;
 
 // bus width assertions
 initial begin
diff --git a/rtl/eth_mac_10g_fifo.v b/rtl/eth_mac_10g_fifo.v
@@ -135,7 +135,7 @@ module eth_mac_10g_fifo #
     input  wire                       cfg_rx_enable
 );
 
-parameter KEEP_WIDTH = DATA_WIDTH/8;
+localparam KEEP_WIDTH = DATA_WIDTH/8;
 
 wire [DATA_WIDTH-1:0]      tx_fifo_axis_tdata;
 wire [KEEP_WIDTH-1:0]      tx_fifo_axis_tkeep;
diff --git a/rtl/eth_mac_1g.v b/rtl/eth_mac_1g.v
@@ -188,8 +188,8 @@ module eth_mac_1g #
     input  wire                         cfg_rx_pfc_en
 );
 
-parameter MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE;
-parameter TX_USER_WIDTH_INT = MAC_CTRL_ENABLE ? (PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1 : 0) + 1 : TX_USER_WIDTH;
+localparam MAC_CTRL_ENABLE = PAUSE_ENABLE || PFC_ENABLE;
+localparam TX_USER_WIDTH_INT = MAC_CTRL_ENABLE ? (PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + 1 : 0) + 1 : TX_USER_WIDTH;
 
 wire [DATA_WIDTH-1:0]         tx_axis_tdata_int;
 wire                          tx_axis_tvalid_int;
diff --git a/rtl/eth_mac_phy_10g_fifo.v b/rtl/eth_mac_phy_10g_fifo.v
@@ -151,7 +151,7 @@ module eth_mac_phy_10g_fifo #
     input  wire                       cfg_rx_prbs31_enable
 );
 
-parameter KEEP_WIDTH = DATA_WIDTH/8;
+localparam KEEP_WIDTH = DATA_WIDTH/8;
 
 wire [DATA_WIDTH-1:0]      tx_fifo_axis_tdata;
 wire [KEEP_WIDTH-1:0]      tx_fifo_axis_tkeep;
diff --git a/rtl/eth_phy_10g_rx_ber_mon.v b/rtl/eth_phy_10g_rx_ber_mon.v
@@ -59,7 +59,7 @@ initial begin
     end
 end
 
-parameter COUNT_WIDTH = $clog2($rtoi(COUNT_125US));
+localparam COUNT_WIDTH = $clog2($rtoi(COUNT_125US));
 
 localparam [1:0]
     SYNC_DATA = 2'b10,
diff --git a/rtl/eth_phy_10g_rx_frame_sync.v b/rtl/eth_phy_10g_rx_frame_sync.v
@@ -53,8 +53,8 @@ module eth_phy_10g_rx_frame_sync #
     output wire                  rx_block_lock
 );
 
-parameter BITSLIP_MAX_CYCLES = BITSLIP_HIGH_CYCLES > BITSLIP_LOW_CYCLES ? BITSLIP_HIGH_CYCLES : BITSLIP_LOW_CYCLES;
-parameter BITSLIP_COUNT_WIDTH = $clog2(BITSLIP_MAX_CYCLES);
+localparam BITSLIP_MAX_CYCLES = BITSLIP_HIGH_CYCLES > BITSLIP_LOW_CYCLES ? BITSLIP_HIGH_CYCLES : BITSLIP_LOW_CYCLES;
+localparam BITSLIP_COUNT_WIDTH = $clog2(BITSLIP_MAX_CYCLES);
 
 // bus width assertions
 initial begin
diff --git a/rtl/eth_phy_10g_rx_watchdog.v b/rtl/eth_phy_10g_rx_watchdog.v
@@ -68,7 +68,7 @@ initial begin
     end
 end
 
-parameter COUNT_WIDTH = $clog2($rtoi(COUNT_125US));
+localparam COUNT_WIDTH = $clog2($rtoi(COUNT_125US));
 
 localparam [1:0]
     SYNC_DATA = 2'b10,
diff --git a/rtl/ip_arb_mux.v b/rtl/ip_arb_mux.v
@@ -113,7 +113,7 @@ module ip_arb_mux #
     output wire [USER_WIDTH-1:0]         m_ip_payload_axis_tuser
 );
 
-parameter CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_S_COUNT = $clog2(S_COUNT);
 
 reg frame_reg = 1'b0, frame_next;
 
diff --git a/rtl/ip_demux.v b/rtl/ip_demux.v
@@ -116,7 +116,7 @@ module ip_demux #
     input  wire [$clog2(M_COUNT)-1:0]    select
 );
 
-parameter CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
 
 reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
 reg drop_reg = 1'b0, drop_ctl, drop_next;
diff --git a/rtl/ip_mux.v b/rtl/ip_mux.v
@@ -115,7 +115,7 @@ module ip_mux #
     input  wire [$clog2(S_COUNT)-1:0]    select
 );
 
-parameter CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_S_COUNT = $clog2(S_COUNT);
 
 reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
 reg frame_reg = 1'b0, frame_next;
diff --git a/rtl/mac_ctrl_rx.v b/rtl/mac_ctrl_rx.v
@@ -109,15 +109,15 @@ module mac_ctrl_rx #
     output wire                          stat_rx_mcf
 );
 
-parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
+localparam BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
 
-parameter HDR_SIZE = 60;
+localparam HDR_SIZE = 60;
 
-parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
+localparam CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
 
-parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
+localparam PTR_WIDTH = $clog2(CYCLE_COUNT);
 
-parameter OFFSET = HDR_SIZE % BYTE_LANES;
+localparam OFFSET = HDR_SIZE % BYTE_LANES;
 
 // check configuration
 initial begin
diff --git a/rtl/mac_ctrl_tx.v b/rtl/mac_ctrl_tx.v
@@ -98,15 +98,15 @@ module mac_ctrl_tx #
     output wire                          stat_tx_mcf
 );
 
-parameter BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
+localparam BYTE_LANES = KEEP_ENABLE ? KEEP_WIDTH : 1;
 
-parameter HDR_SIZE = 60;
+localparam HDR_SIZE = 60;
 
-parameter CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
+localparam CYCLE_COUNT = (HDR_SIZE+BYTE_LANES-1)/BYTE_LANES;
 
-parameter PTR_WIDTH = $clog2(CYCLE_COUNT);
+localparam PTR_WIDTH = $clog2(CYCLE_COUNT);
 
-parameter OFFSET = HDR_SIZE % BYTE_LANES;
+localparam OFFSET = HDR_SIZE % BYTE_LANES;
 
 // check configuration
 initial begin
diff --git a/rtl/ptp_clock.v b/rtl/ptp_clock.v
@@ -94,7 +94,7 @@ module ptp_clock #
     output wire                       output_pps
 );
 
-parameter INC_NS_WIDTH = $clog2(2**PERIOD_NS_WIDTH + 2**OFFSET_NS_WIDTH + 2**DRIFT_NS_WIDTH);
+localparam INC_NS_WIDTH = $clog2(2**PERIOD_NS_WIDTH + 2**OFFSET_NS_WIDTH + 2**DRIFT_NS_WIDTH);
 
 localparam [30:0] NS_PER_S = 31'd1_000_000_000;
 
diff --git a/rtl/ssio_sdr_in_diff.v b/rtl/ssio_sdr_in_diff.v
@@ -101,7 +101,6 @@ endgenerate
 
 ssio_sdr_in #(
     .TARGET(TARGET),
-    .IODDR_STYLE(IODDR_STYLE),
     .CLOCK_INPUT_STYLE(CLOCK_INPUT_STYLE),
     .WIDTH(WIDTH)
 )
diff --git a/rtl/udp_checksum_gen.v b/rtl/udp_checksum_gen.v
@@ -140,7 +140,7 @@ header fields in parallel along with the UDP payload in a separate AXI stream.
 
 */
 
-parameter HEADER_FIFO_ADDR_WIDTH = $clog2(HEADER_FIFO_DEPTH);
+localparam HEADER_FIFO_ADDR_WIDTH = $clog2(HEADER_FIFO_DEPTH);
 
 localparam [2:0]
     STATE_IDLE = 3'd0,
diff --git a/rtl/udp_checksum_gen_64.v b/rtl/udp_checksum_gen_64.v
@@ -142,7 +142,7 @@ header fields in parallel along with the UDP payload in a separate AXI stream.
 
 */
 
-parameter HEADER_FIFO_ADDR_WIDTH = $clog2(HEADER_FIFO_DEPTH);
+localparam HEADER_FIFO_ADDR_WIDTH = $clog2(HEADER_FIFO_DEPTH);
 
 localparam [2:0]
     STATE_IDLE = 3'd0,
diff --git a/rtl/udp_demux.v b/rtl/udp_demux.v
@@ -124,7 +124,7 @@ module udp_demux #
     input  wire [$clog2(M_COUNT)-1:0]    select
 );
 
-parameter CL_M_COUNT = $clog2(M_COUNT);
+localparam CL_M_COUNT = $clog2(M_COUNT);
 
 reg [CL_M_COUNT-1:0] select_reg = {CL_M_COUNT{1'b0}}, select_ctl, select_next;
 reg drop_reg = 1'b0, drop_ctl, drop_next;
diff --git a/rtl/udp_mux.v b/rtl/udp_mux.v
@@ -123,7 +123,7 @@ module udp_mux #
     input  wire [$clog2(S_COUNT)-1:0]    select
 );
 
-parameter CL_S_COUNT = $clog2(S_COUNT);
+localparam CL_S_COUNT = $clog2(S_COUNT);
 
 reg [CL_S_COUNT-1:0] select_reg = 2'd0, select_next;
 reg frame_reg = 1'b0, frame_next;
