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1 parent a5c4b22 commit e9be3f9Copy full SHA for e9be3f9
rtl/rgmii_phy_if.v
@@ -34,18 +34,18 @@ THE SOFTWARE.
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module rgmii_phy_if #
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(
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// target ("SIM", "GENERIC", "XILINX", "ALTERA")
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- parameter TARGET = "GENERIC",
+ parameter TARGET = "XILINX",
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// IODDR style ("IODDR", "IODDR2")
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// Use IODDR for Virtex-4, Virtex-5, Virtex-6, 7 Series, Ultrascale
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// Use IODDR2 for Spartan-6
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- parameter IODDR_STYLE = "IODDR2",
+ parameter IODDR_STYLE = "IODDR",
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// Clock input style ("BUFG", "BUFR", "BUFIO", "BUFIO2")
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// Use BUFR for Virtex-6, 7-series
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// Use BUFG for Virtex-5, Spartan-6, Ultrascale
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- parameter CLOCK_INPUT_STYLE = "BUFG",
+ parameter CLOCK_INPUT_STYLE = "BUFIO",
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// Use 90 degree clock for RGMII transmit ("TRUE", "FALSE")
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parameter USE_CLK90 = "TRUE",
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- parameter INSERT_BUFFERS = "TRUE"
+ parameter INSERT_BUFFERS = "FALSE"
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)
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// Reset, synchronous to gmii_gtx_clk
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