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Add rx_axis_clk reference
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rtl/eth_mac_1g.v

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,8 +49,10 @@ module eth_mac_1g #
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)
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(
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input wire tx_clk,
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// Copy of rx clock to appease xilinx interfaces
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output wire rx_axis_clk,
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/*
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* AXI input
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*/
@@ -208,6 +210,8 @@ wire rx_axis_tlast_int;
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wire [RX_USER_WIDTH-1:0] rx_axis_tuser_int;
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assign gmii_gtx_clk = tx_clk;
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assign rx_axis_clk = gmii_rx_clk;
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axis_gmii_rx #(
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.DATA_WIDTH(DATA_WIDTH),
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.PTP_TS_ENABLE(PTP_TS_ENABLE),

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