From 5053506e6c80d32d02da39c36fece5cc5f63d10a Mon Sep 17 00:00:00 2001 From: kavitha Date: Tue, 18 Feb 2025 11:04:19 +0000 Subject: [PATCH 1/3] Exclude crc form frame --- rtl/axis_gmii_rx.v | 28 ++++++++++++++++------------ 1 file changed, 16 insertions(+), 12 deletions(-) diff --git a/rtl/axis_gmii_rx.v b/rtl/axis_gmii_rx.v index 9b4f30d66..853bcc592 100644 --- a/rtl/axis_gmii_rx.v +++ b/rtl/axis_gmii_rx.v @@ -125,10 +125,14 @@ reg gmii_rx_er_d2 = 1'b0; reg gmii_rx_er_d3 = 1'b0; reg gmii_rx_er_d4 = 1'b0; -reg [DATA_WIDTH-1:0] m_axis_tdata_reg = {DATA_WIDTH{1'b0}}, m_axis_tdata_next; -reg m_axis_tvalid_reg = 1'b0, m_axis_tvalid_next; -reg m_axis_tlast_reg = 1'b0, m_axis_tlast_next; -reg m_axis_tuser_reg = 1'b0, m_axis_tuser_next; +reg [DATA_WIDTH-1:0] m_axis_tdata_reg [4:0]; +reg [DATA_WIDTH-1:0] m_axis_tdata_next; +reg [4:0] m_axis_tvalid_reg = 5'b0; +reg m_axis_tvalid_next; +reg [4:0] m_axis_tlast_reg = 5'b0; +reg m_axis_tlast_next; +reg [4:0] m_axis_tuser_reg = 5'b0; +reg m_axis_tuser_next; reg start_packet_int_reg = 1'b0; reg start_packet_reg = 1'b0; @@ -140,10 +144,10 @@ reg [PTP_TS_WIDTH-1:0] ptp_ts_reg = 0; reg [31:0] crc_state = 32'hFFFFFFFF; wire [31:0] crc_next; -assign m_axis_tdata = m_axis_tdata_reg; -assign m_axis_tvalid = m_axis_tvalid_reg; -assign m_axis_tlast = m_axis_tlast_reg; -assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, m_axis_tuser_reg} : m_axis_tuser_reg; +assign m_axis_tdata = m_axis_tdata_reg[4]; +assign m_axis_tvalid = m_axis_tvalid_reg[4] & ~(|m_axis_tlast_reg[4:1]); +assign m_axis_tlast = m_axis_tlast_reg[0]; +assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, m_axis_tuser_reg[4]} : m_axis_tuser_reg[4]; assign start_packet = start_packet_reg; assign error_bad_frame = error_bad_frame_reg; @@ -247,10 +251,10 @@ end always @(posedge clk) begin state_reg <= state_next; - m_axis_tdata_reg <= m_axis_tdata_next; - m_axis_tvalid_reg <= m_axis_tvalid_next; - m_axis_tlast_reg <= m_axis_tlast_next; - m_axis_tuser_reg <= m_axis_tuser_next; + m_axis_tdata_reg <= {m_axis_tdata_reg[3:0],m_axis_tdata_next}; + m_axis_tvalid_reg <= {m_axis_tvalid_reg[3:0],m_axis_tvalid_next}; + m_axis_tlast_reg <= {m_axis_tlast_reg[3:0],m_axis_tlast_next}; + m_axis_tuser_reg <= {m_axis_tuser_reg[3:0],m_axis_tuser_next}; start_packet_int_reg <= 1'b0; start_packet_reg <= 1'b0; From 0238e5fa0ed59866276f8c7940098d85f119a842 Mon Sep 17 00:00:00 2001 From: kavitha Date: Thu, 20 Feb 2025 08:57:41 +0000 Subject: [PATCH 2/3] bug fix --- rtl/axis_gmii_rx.v | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/rtl/axis_gmii_rx.v b/rtl/axis_gmii_rx.v index 853bcc592..4737cc69e 100644 --- a/rtl/axis_gmii_rx.v +++ b/rtl/axis_gmii_rx.v @@ -125,7 +125,7 @@ reg gmii_rx_er_d2 = 1'b0; reg gmii_rx_er_d3 = 1'b0; reg gmii_rx_er_d4 = 1'b0; -reg [DATA_WIDTH-1:0] m_axis_tdata_reg [4:0]; +reg [(5*DATA_WIDTH)-1:0] m_axis_tdata_reg; reg [DATA_WIDTH-1:0] m_axis_tdata_next; reg [4:0] m_axis_tvalid_reg = 5'b0; reg m_axis_tvalid_next; @@ -144,7 +144,7 @@ reg [PTP_TS_WIDTH-1:0] ptp_ts_reg = 0; reg [31:0] crc_state = 32'hFFFFFFFF; wire [31:0] crc_next; -assign m_axis_tdata = m_axis_tdata_reg[4]; +assign m_axis_tdata = m_axis_tdata_reg[(5*DATA_WIDTH)-1:4*DATA_WIDTH]; assign m_axis_tvalid = m_axis_tvalid_reg[4] & ~(|m_axis_tlast_reg[4:1]); assign m_axis_tlast = m_axis_tlast_reg[0]; assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, m_axis_tuser_reg[4]} : m_axis_tuser_reg[4]; @@ -251,7 +251,7 @@ end always @(posedge clk) begin state_reg <= state_next; - m_axis_tdata_reg <= {m_axis_tdata_reg[3:0],m_axis_tdata_next}; + m_axis_tdata_reg <= {m_axis_tdata_reg[(4*DATA_WIDTH)-1:0],m_axis_tdata_next}; m_axis_tvalid_reg <= {m_axis_tvalid_reg[3:0],m_axis_tvalid_next}; m_axis_tlast_reg <= {m_axis_tlast_reg[3:0],m_axis_tlast_next}; m_axis_tuser_reg <= {m_axis_tuser_reg[3:0],m_axis_tuser_next}; From 5a5f47d9008b062ff85f0ea498d8239ffffbec1b Mon Sep 17 00:00:00 2001 From: kavitha Date: Thu, 20 Feb 2025 10:43:55 +0000 Subject: [PATCH 3/3] added crc parameter --- rtl/axis_gmii_rx.v | 9 +++++---- rtl/eth_mac_1g.v | 6 ++++-- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/rtl/axis_gmii_rx.v b/rtl/axis_gmii_rx.v index 4737cc69e..66f3fb4c9 100644 --- a/rtl/axis_gmii_rx.v +++ b/rtl/axis_gmii_rx.v @@ -36,6 +36,7 @@ module axis_gmii_rx # parameter DATA_WIDTH = 8, parameter PTP_TS_ENABLE = 0, parameter PTP_TS_WIDTH = 96, + parameter EXCLUDE_CRC = 0, parameter USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1 ) ( @@ -144,10 +145,10 @@ reg [PTP_TS_WIDTH-1:0] ptp_ts_reg = 0; reg [31:0] crc_state = 32'hFFFFFFFF; wire [31:0] crc_next; -assign m_axis_tdata = m_axis_tdata_reg[(5*DATA_WIDTH)-1:4*DATA_WIDTH]; -assign m_axis_tvalid = m_axis_tvalid_reg[4] & ~(|m_axis_tlast_reg[4:1]); -assign m_axis_tlast = m_axis_tlast_reg[0]; -assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, m_axis_tuser_reg[4]} : m_axis_tuser_reg[4]; +assign m_axis_tdata = EXCLUDE_CRC ? m_axis_tdata_reg[(5*DATA_WIDTH)-1:4*DATA_WIDTH] : m_axis_tdata_reg[DATA_WIDTH-1:0]; +assign m_axis_tvalid = EXCLUDE_CRC ? m_axis_tvalid_reg[4] & ~(|m_axis_tlast_reg[4:1]) : m_axis_tvalid_reg[0]; +assign m_axis_tlast = m_axis_tlast_reg[0]; +assign m_axis_tuser = PTP_TS_ENABLE ? {ptp_ts_reg, EXCLUDE_CRC? m_axis_tuser_reg[4] : m_axis_tuser_reg[0]} : (EXCLUDE_CRC ? m_axis_tuser_reg[4] : m_axis_tuser_reg[0]); assign start_packet = start_packet_reg; assign error_bad_frame = error_bad_frame_reg; diff --git a/rtl/eth_mac_1g.v b/rtl/eth_mac_1g.v index 7165a673b..77337ca3b 100644 --- a/rtl/eth_mac_1g.v +++ b/rtl/eth_mac_1g.v @@ -45,7 +45,8 @@ module eth_mac_1g # parameter TX_USER_WIDTH = (PTP_TS_ENABLE ? (TX_PTP_TAG_ENABLE ? TX_PTP_TAG_WIDTH : 0) + (TX_PTP_TS_CTRL_IN_TUSER ? 1 : 0) : 0) + 1, parameter RX_USER_WIDTH = (PTP_TS_ENABLE ? PTP_TS_WIDTH : 0) + 1, parameter PFC_ENABLE = 0, - parameter PAUSE_ENABLE = PFC_ENABLE + parameter PAUSE_ENABLE = PFC_ENABLE, + parameter EXCLUDE_CRC = 0 ) ( input wire rx_clk, @@ -206,7 +207,8 @@ axis_gmii_rx #( .DATA_WIDTH(DATA_WIDTH), .PTP_TS_ENABLE(PTP_TS_ENABLE), .PTP_TS_WIDTH(PTP_TS_WIDTH), - .USER_WIDTH(RX_USER_WIDTH) + .USER_WIDTH(RX_USER_WIDTH), + .EXCLUDE_CRC(EXCLUDE_CRC) ) axis_gmii_rx_inst ( .clk(rx_clk),