riscv_RocketChip_0_synth_1 Synthesis failed !!

[Apurba-IITB]

I was trying to generate FPGA bit file with the below configuration:

make CONFIG=rocket32s1 BOARD=arty-a7-100t bitstream

I have tried different RISC-V Cores and FPGA options with vivado 2021.2 & 2022.2 but got same warning and synthesis failed due to same reasons.
32-bit small RISC-V cores:
rocket32s1 - 1 core
rocket32s2 - 2 cores
rocket32s4 - 4 cores
rocket32s8 - 8 cores
rocket32s16 - 16 cores

BOARD=genesys2
BOARD=nexys-a7-100t
BOARD=arty-a7-100t

[Synth 8-4767] Trying to implement RAM 'ram_tl_state_size_reg' in registers. Block RAM or DRAM implementation is not possible; see log for reasons.
Reason is one or more of the following :
1: Write port has constant address.
2: No valid read/write found for RAM.
2: Only 1 word in RAM

N.B. I am working with both 64-bit big RISC-V cores and 64-bit Sonic BOOM cores without any problem. All the 64 bit cores work fine!!