msm8909gfx

Author: exkc

arch/arm/boot/dts/qcom/qcom-msm8909.dtsi

@@ -195,7 +195,6 @@
 		compatible = "arm,cortex-a7-pmu";
 		interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 	};
-
 	reserved-memory {
 		#address-cells = <1>;
 		#size-cells = <1>;
@@ -382,7 +381,74 @@
 		#size-cells = <1>;
 		ranges;
 
-		rng@22000 {
+		
+		gpu_iommu: iommu@1f08000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#iommu-cells = <1>;
+			compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+			ranges = <0 0x01f08000 0x10000>;
+			clocks = <&gcc GCC_SMMU_CFG_CLK>,
+				 <&gcc GCC_GFX_TCU_CLK>;
+			clock-names = "iface", "bus";
+			qcom,iommu-secure-id = <18>;
+
+			/* GFX3D_USER */
+			iommu-ctx@1000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x1000 0x1000>;
+				interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+			};
+
+			/* GFX3D_PRIV */
+			iommu-ctx@2000 {
+				compatible = "qcom,msm-iommu-v1-ns";
+				reg = <0x2000 0x1000>;
+				interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gpu: gpu@1c00000 {
+			compatible = "amd,imageon-304.0", "amd,imageon";
+			reg = <0x01c00000 0x10000
+		       0x01c10000 0x10000
+		       0x0005c00c 0x8>;
+			reg-names = "kgsl_3d0_reg_memory";
+			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "kgsl_3d0_irq";
+			clock-names =
+			    "core",
+			    "iface",
+			    "mem_iface",
+			    "alt_mem_iface",
+			    "gfx3d";
+			clocks =
+			    <&gcc GCC_OXILI_GFX3D_CLK>,
+			    <&gcc GCC_OXILI_AHB_CLK>,
+			    <&gcc GCC_BIMC_GFX_CLK>,
+			    <&gcc GCC_BIMC_GPU_CLK>,
+			    <&gcc GFX3D_CLK_SRC>;
+			power-domains = <&gcc OXILI_GDSC>;
+			operating-points-v2 = <&gpu_opp_table>;
+			iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
+			#cooling-cells = <2>;
+			qcom,force-iommu;
+
+			status = "okay";
+
+			gpu_opp_table: opp-table {
+				compatible = "operating-points-v2";
+
+				opp-456000000 {
+					opp-hz = /bits/ 64 <456000000>;
+				};
+				opp-19200000 {
+					opp-hz = /bits/ 64 <19200000>;
+				};
+			};
+		};
+
+rng@22000 {
 			compatible = "qcom,prng";
 			reg = <0x00022000 0x200>;
 			clocks = <&gcc GCC_PRNG_AHB_CLK>;

drivers/gpu/drm/msm/adreno/a3xx_catalog.c

@@ -19,6 +19,17 @@ static const struct adreno_info a3xx_gpus[] = {
 		.gmem  = SZ_128K,
 		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
 		.init  = a3xx_gpu_init,
+	}, {
+		.chip_ids = ADRENO_CHIP_IDS(0x03000400),
+		.family = ADRENO_3XX,
+		.revn  = 304,
+		.fw = {
+			[ADRENO_FW_PM4] = "a300_pm4.fw",
+			[ADRENO_FW_PFP] = "a300_pfp.fw",
+		},
+		.gmem  = (SZ_64K + SZ_32K),
+		.inactive_period = DRM_MSM_INACTIVE_PERIOD,
+		.init  = a3xx_gpu_init,
 	}, {
 		.chip_ids = ADRENO_CHIP_IDS(0x03000520),
 		.family = ADRENO_3XX,

drivers/gpu/drm/msm/adreno/a3xx_gpu.c

@@ -210,6 +210,8 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
 		 */
 		gpu_write(gpu, REG_A3XX_VBIF_CLKON, 0x00000001);
 
+	} else if (adreno_is_a304(adreno_gpu)) {
+		gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003);
 	} else {
 		BUG();
 	}
@@ -242,6 +244,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
 
 	/* Enable Clock gating: */
 	if (adreno_is_a305b(adreno_gpu) ||
+	    adreno_is_a304(adreno_gpu) ||
 	    adreno_is_a306(adreno_gpu) ||
 	    adreno_is_a306a(adreno_gpu))
 		gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa);
@@ -341,6 +344,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu)
 
 	/* CP ROQ queue sizes (bytes) - RB:16, ST:16, IB1:32, IB2:64 */
 	if (adreno_is_a305(adreno_gpu) ||
+	    adreno_is_a304(adreno_gpu) ||
 	    adreno_is_a306(adreno_gpu) ||
 	    adreno_is_a306a(adreno_gpu) ||
 	    adreno_is_a320(adreno_gpu)) {

drivers/gpu/drm/msm/adreno/adreno_gpu.h

@@ -294,6 +294,11 @@ static inline bool adreno_is_a225(const struct adreno_gpu *gpu)
 	return adreno_is_revn(gpu, 225);
 }
 
+static inline bool adreno_is_a304(const struct adreno_gpu *gpu)
+{
+	return adreno_is_revn(gpu, 304);
+}
+
 static inline bool adreno_is_a305(const struct adreno_gpu *gpu)
 {
 	return adreno_is_revn(gpu, 305);

mesapatch

@@ -0,0 +1,25 @@
+From dc6e6d7a2bedcc34d59e76f08ca4362369438f32 Mon Sep 17 00:00:00 2028
+From: exkc <exkc@exkc.moe>
+Date: Tue, 28 May 2024 14:15:09 -0700
+Subject: [PATCH] freedreno: Enable Adreno 304
+
+---
+ src/freedreno/common/freedreno_devices.py | 1 +
+ 1 file changed, 1 insertion(+)
+
+diff --git a/src/freedreno/common/freedreno_devices.py b/src/freedreno/common/freedreno_devices.py
+index 2d38d01862b7f..b3ad9fbc4b9f0 100644
+--- a/src/freedreno/common/freedreno_devices.py
++++ b/src/freedreno/common/freedreno_devices.py
+@@ -217,6 +217,7 @@ add_gpus([
+         GPUId(320),
+         GPUId(330),
+         GPUId(chip_id=0x03000512, name="FD305B"),
+         GPUId(chip_id=0x03000620, name="FD306A"),
++        GPUId(chip_id=0x03000400, name="QwQ_GPU"),
+     ], GPUInfo(
+         CHIP.A3XX,
+         gmem_align_w = 32,  gmem_align_h = 32,
+-- 
+GitLab
+