refactor(core/assembler): extract file for codes

Author: exuanbo

src/core/assembler/assembler.ts

@@ -3,6 +3,7 @@ import { expectNever } from 'ts-expect'
 import { compose } from '@/common/utils/context'
 import { invariant } from '@/common/utils/invariant'
 
+import { Register } from '../code'
 import { AssemblerState, createAssemblerState } from './assembler.state'
 import { getSize, hasIdentifier, type WithIdentifier } from './assembler.utils'
 import {
@@ -14,7 +15,6 @@ import {
 } from './assemblyunit'
 import * as AST from './ast'
 import { AssemblerError, type AssemblyError, ErrorCode, ParserError, Severity } from './errors'
-import * as InstrSet from './instrset'
 import { resolveOpcode } from './instrset.utils'
 import { createLexer } from './lexer'
 import { createParser } from './parser'
@@ -254,7 +254,7 @@ function resolveIdentifier({ children: [name], loc }: AST.Identifier): number {
 }
 
 function resolveRegister({ children: [name] }: AST.Register): number {
-  return InstrSet.Register[name]
+  return Register[name]
 }
 
 function resolveImmediate({ children: [value], loc }: AST.Immediate): number {

src/core/assembler/instrset.ts

@@ -1,3 +1,4 @@
+import { Opcode } from '../code'
 import * as AST from './ast'
 
 export type OperandPattern =
@@ -7,158 +8,151 @@ export type OperandPattern =
     children: OperandPattern[]
   }
 
-export const patterns: Record<AST.Mnemonic, [number, OperandPattern[]][]> = {
+export const patterns: Record<AST.Mnemonic, [Opcode, OperandPattern[]][]> = {
+  HALT: [
+    [Opcode.HALT, []],
+  ],
   ADD: [
-    [0xa0, [AST.NodeType.Register, AST.NodeType.Register]],
-    [0xb0, [AST.NodeType.Register, AST.NodeType.Immediate]],
+    [Opcode.ADD_REG_REG, [AST.NodeType.Register, AST.NodeType.Register]],
+    [Opcode.ADD_REG_IMM, [AST.NodeType.Register, AST.NodeType.Immediate]],
   ],
   SUB: [
-    [0xa1, [AST.NodeType.Register, AST.NodeType.Register]],
-    [0xb1, [AST.NodeType.Register, AST.NodeType.Immediate]],
+    [Opcode.SUB_REG_REG, [AST.NodeType.Register, AST.NodeType.Register]],
+    [Opcode.SUB_REG_IMM, [AST.NodeType.Register, AST.NodeType.Immediate]],
   ],
   MUL: [
-    [0xa2, [AST.NodeType.Register, AST.NodeType.Register]],
-    [0xb2, [AST.NodeType.Register, AST.NodeType.Immediate]],
+    [Opcode.MUL_REG_REG, [AST.NodeType.Register, AST.NodeType.Register]],
+    [Opcode.MUL_REG_IMM, [AST.NodeType.Register, AST.NodeType.Immediate]],
   ],
   DIV: [
-    [0xa3, [AST.NodeType.Register, AST.NodeType.Register]],
-    [0xb3, [AST.NodeType.Register, AST.NodeType.Immediate]],
+    [Opcode.DIV_REG_REG, [AST.NodeType.Register, AST.NodeType.Register]],
+    [Opcode.DIV_REG_IMM, [AST.NodeType.Register, AST.NodeType.Immediate]],
   ],
   INC: [
-    [0xa4, [AST.NodeType.Register]],
+    [Opcode.INC_REG, [AST.NodeType.Register]],
   ],
   DEC: [
-    [0xa5, [AST.NodeType.Register]],
+    [Opcode.DEC_REG, [AST.NodeType.Register]],
   ],
   MOD: [
-    [0xa6, [AST.NodeType.Register, AST.NodeType.Register]],
-    [0xb6, [AST.NodeType.Register, AST.NodeType.Immediate]],
+    [Opcode.MOD_REG_REG, [AST.NodeType.Register, AST.NodeType.Register]],
+    [Opcode.MOD_REG_IMM, [AST.NodeType.Register, AST.NodeType.Immediate]],
   ],
   AND: [
-    [0xaa, [AST.NodeType.Register, AST.NodeType.Register]],
-    [0xba, [AST.NodeType.Register, AST.NodeType.Immediate]],
+    [Opcode.AND_REG_REG, [AST.NodeType.Register, AST.NodeType.Register]],
+    [Opcode.AND_REG_IMM, [AST.NodeType.Register, AST.NodeType.Immediate]],
   ],
   OR: [
-    [0xab, [AST.NodeType.Register, AST.NodeType.Register]],
-    [0xbb, [AST.NodeType.Register, AST.NodeType.Immediate]],
+    [Opcode.OR_REG_REG, [AST.NodeType.Register, AST.NodeType.Register]],
+    [Opcode.OR_REG_IMM, [AST.NodeType.Register, AST.NodeType.Immediate]],
   ],
   XOR: [
-    [0xac, [AST.NodeType.Register, AST.NodeType.Register]],
-    [0xbc, [AST.NodeType.Register, AST.NodeType.Immediate]],
+    [Opcode.XOR_REG_REG, [AST.NodeType.Register, AST.NodeType.Register]],
+    [Opcode.XOR_REG_IMM, [AST.NodeType.Register, AST.NodeType.Immediate]],
   ],
   NOT: [
-    [0xad, [AST.NodeType.Register]],
+    [Opcode.NOT_REG, [AST.NodeType.Register]],
   ],
   ROL: [
-    [0x9a, [AST.NodeType.Register]],
+    [Opcode.ROL_REG, [AST.NodeType.Register]],
   ],
   ROR: [
-    [0x9b, [AST.NodeType.Register]],
+    [Opcode.ROR_REG, [AST.NodeType.Register]],
   ],
   SHL: [
-    [0x9c, [AST.NodeType.Register]],
+    [Opcode.SHL_REG, [AST.NodeType.Register]],
   ],
   SHR: [
-    [0x9d, [AST.NodeType.Register]],
+    [Opcode.SHR_REG, [AST.NodeType.Register]],
   ],
   JMP: [
-    [0xc0, [AST.NodeType.Identifier]],
+    [Opcode.JMP, [AST.NodeType.Identifier]],
   ],
   JZ: [
-    [0xc1, [AST.NodeType.Identifier]],
+    [Opcode.JZ, [AST.NodeType.Identifier]],
   ],
   JNZ: [
-    [0xc2, [AST.NodeType.Identifier]],
+    [Opcode.JNZ, [AST.NodeType.Identifier]],
   ],
   JS: [
-    [0xc3, [AST.NodeType.Identifier]],
+    [Opcode.JS, [AST.NodeType.Identifier]],
   ],
   JNS: [
-    [0xc4, [AST.NodeType.Identifier]],
+    [Opcode.JNS, [AST.NodeType.Identifier]],
   ],
   JO: [
-    [0xc5, [AST.NodeType.Identifier]],
+    [Opcode.JO, [AST.NodeType.Identifier]],
   ],
   JNO: [
-    [0xc6, [AST.NodeType.Identifier]],
+    [Opcode.JNO, [AST.NodeType.Identifier]],
   ],
   MOV: [
-    [0xd0, [AST.NodeType.Register, AST.NodeType.Immediate]],
-    [0xd1, [
+    [Opcode.MOV_REG_IMM, [AST.NodeType.Register, AST.NodeType.Immediate]],
+    [Opcode.MOV_REG_ADDR, [
       AST.NodeType.Register,
       { type: AST.NodeType.MemoryOperand, children: [AST.NodeType.Immediate] },
     ]],
-    [0xd2, [
+    [Opcode.MOV_ADDR_REG, [
       { type: AST.NodeType.MemoryOperand, children: [AST.NodeType.Immediate] },
       AST.NodeType.Register,
     ]],
-    [0xd3, [
+    [Opcode.MOV_REG_REG_ADDR, [
       AST.NodeType.Register,
       { type: AST.NodeType.MemoryOperand, children: [AST.NodeType.Register] },
     ]],
-    [0xd4, [
+    [Opcode.MOV_REG_ADDR_REG, [
       { type: AST.NodeType.MemoryOperand, children: [AST.NodeType.Register] },
       AST.NodeType.Register,
     ]],
   ],
   CMP: [
-    [0xda, [AST.NodeType.Register, AST.NodeType.Register]],
-    [0xdb, [AST.NodeType.Register, AST.NodeType.Immediate]],
-    [0xdc, [
+    [Opcode.CMP_REG_REG, [AST.NodeType.Register, AST.NodeType.Register]],
+    [Opcode.CMP_REG_IMM, [AST.NodeType.Register, AST.NodeType.Immediate]],
+    [Opcode.CMP_REG_ADDR, [
       AST.NodeType.Register,
       { type: AST.NodeType.MemoryOperand, children: [AST.NodeType.Immediate] },
     ]],
   ],
   PUSH: [
-    [0xe0, [AST.NodeType.Register]],
+    [Opcode.PUSH_REG, [AST.NodeType.Register]],
   ],
   POP: [
-    [0xe1, [AST.NodeType.Register]],
+    [Opcode.POP_REG, [AST.NodeType.Register]],
   ],
   PUSHF: [
-    [0xea, []],
+    [Opcode.PUSHF, []],
   ],
   POPF: [
-    [0xeb, []],
+    [Opcode.POPF, []],
   ],
   CALL: [
-    [0xca, [AST.NodeType.Immediate]],
+    [Opcode.CALL_ADDR, [AST.NodeType.Immediate]],
   ],
   RET: [
-    [0xcb, []],
+    [Opcode.RET, []],
   ],
   INT: [
-    [0xcc, [AST.NodeType.Immediate]],
+    [Opcode.INT_ADDR, [AST.NodeType.Immediate]],
   ],
   IRET: [
-    [0xcd, []],
+    [Opcode.IRET, []],
   ],
   IN: [
-    [0xf0, [AST.NodeType.Immediate]],
+    [Opcode.IN_IMM, [AST.NodeType.Immediate]],
   ],
   OUT: [
-    [0xf1, [AST.NodeType.Immediate]],
-  ],
-  HALT: [
-    [0x00, []],
+    [Opcode.OUT_IMM, [AST.NodeType.Immediate]],
   ],
   STI: [
-    [0xfc, []],
+    [Opcode.STI, []],
   ],
   CLI: [
-    [0xfd, []],
+    [Opcode.CLI, []],
   ],
   CLO: [
-    [0xfe, []],
+    [Opcode.CLO, []],
   ],
   NOP: [
-    [0xff, []],
+    [Opcode.NOP, []],
   ],
 }
-
-export enum Register {
-  AL = 0x00,
-  BL = 0x01,
-  CL = 0x02,
-  DL = 0x03,
-}

src/core/code.ts

@@ -0,0 +1,88 @@
+export enum Opcode {
+  HALT = 0x00,
+
+  // Direct Arithmetic
+  ADD_REG_REG = 0xa0,
+  SUB_REG_REG = 0xa1,
+  MUL_REG_REG = 0xa2,
+  DIV_REG_REG = 0xa3,
+  INC_REG = 0xa4,
+  DEC_REG = 0xa5,
+  MOD_REG_REG = 0xa6,
+  AND_REG_REG = 0xaa,
+  OR_REG_REG = 0xab,
+  XOR_REG_REG = 0xac,
+  NOT_REG = 0xad,
+  ROL_REG = 0x9a,
+  ROR_REG = 0x9b,
+  SHL_REG = 0x9c,
+  SHR_REG = 0x9d,
+
+  // Immediate Arithmetic
+  ADD_REG_IMM = 0xb0,
+  SUB_REG_IMM = 0xb1,
+  MUL_REG_IMM = 0xb2,
+  DIV_REG_IMM = 0xb3,
+  MOD_REG_IMM = 0xb6,
+  AND_REG_IMM = 0xba,
+  OR_REG_IMM = 0xbb,
+  XOR_REG_IMM = 0xbc,
+
+  // Jump
+  JMP = 0xc0,
+  JZ = 0xc1,
+  JNZ = 0xc2,
+  JS = 0xc3,
+  JNS = 0xc4,
+  JO = 0xc5,
+  JNO = 0xc6,
+
+  // Immediate Move
+  MOV_REG_IMM = 0xd0,
+
+  // Direct Move
+  MOV_REG_ADDR = 0xd1,
+  MOV_ADDR_REG = 0xd2,
+
+  // Indirect Move
+  MOV_REG_REG_ADDR = 0xd3,
+  MOV_REG_ADDR_REG = 0xd4,
+
+  // Direct Register Comparison
+  CMP_REG_REG = 0xda,
+
+  // Immediate Comparison
+  CMP_REG_IMM = 0xdb,
+
+  // Direct Memory Comparison
+  CMP_REG_ADDR = 0xdc,
+
+  // Stack
+  PUSH_REG = 0xe0,
+  POP_REG = 0xe1,
+  PUSHF = 0xea,
+  POPF = 0xeb,
+
+  // Procedures and Interrupts
+  CALL_ADDR = 0xca,
+  RET = 0xcb,
+  INT_ADDR = 0xcc,
+  IRET = 0xcd,
+
+  // Input and Output
+  IN_IMM = 0xf0,
+  OUT_IMM = 0xf1,
+
+  // Miscellaneous
+  STI = 0xfc,
+  CLI = 0xfd,
+  CLO = 0xfe,
+  NOP = 0xff,
+}
+
+export enum Register {
+  AL = 0x00,
+  BL = 0x01,
+  CL = 0x02,
+  DL = 0x03,
+}