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developers: content moved to documentation site
Signed-off-by: Unai Martinez-Corral <umartinezcorral@antmicro.com>
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‎index.hbs‎

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<span class="underline">How it works</span>
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</h2>
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<p class="diagrams__paragraph_intro">
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To understand how F4PGA works, it is best to start with an overview of <br />
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the general EDA tooling ecosystem and then proceed to see what <br />
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the F4PGA project consists of.
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To understand how F4PGA works, it is best to start with an overview of the general <br />
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EDA tooling ecosystem and then proceed to see what the F4PGA project consists of. <br />
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See: <a href="https://f4pga.readthedocs.io/en/latest/how.html#eda-tooling-ecosystem#eda-tooling-ecosystem">EDA Tooling Ecosystem</a> and <a href="https://f4pga.readthedocs.io/en/latest/how.html#eda-tooling-ecosystem#project-structure">Project structure</a>.
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</p>
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<div class="diagrams__diagram" id="eda-ecosystem">
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<h3 class="diagram__header">
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EDA Tooling Ecosystem
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</h3>
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<div class="diagrams__content">
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<div class="diagrams__paragraph">
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<p>
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For both ASIC- and FPGA-oriented EDA tooling,
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there are three major areas:
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</p>
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<ul>
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<li> hardware description </li>
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<li> frontend </li>
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<li> backend </li>
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</ul>
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</div>
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<p class="diagrams__paragraph">
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While there are a number of open hardware description languages, such as
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Verilog, VHDL, Chisel, Migen and Amaranth HDL, the frontend and backend
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tooling has been lacking established standard, vendor-neutral solutions.
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F4PGA focuses on filling this gap.
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</p>
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</div>
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<div class="diagram__diagram">
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<img src="assets/img/EDA.svg" alt="" />
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</div>
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</div>
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<div class="diagrams__diagram" id="structure">
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<h3 class="diagram__header">
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F4PGA project structure
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</h3>
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<div class="diagrams__content">
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<p class="diagrams__paragraph">
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To become a complete FOSS FPGA toolchain, F4PGA needs a number of
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tools and projects to be in place to provide an end-to-end flow.
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Thus, F4PGA serves as an umbrella framework for several activities,
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the central of which focuses on the creation of FPGA
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F4PGA Architecture Definitions, i.e. documentation of how specific
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FPGAs work internally.
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</p>
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<p class="diagrams__paragraph">
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Those definitions and serve as input to backend tools like nextpnr and
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Verilog to Routing, and frontend tools like Yosys. They are created
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within separate collaborating projects targeting different FPGAs -
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<a href="https://github.com/F4PGA/prjxray">Project X-Ray</a> for Xilinx 7-Series,
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<a href="https://github.com/F4PGA/icestorm">Project IceStorm</a> for Lattice iCE40 and
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<a href="https://github.com/F4PGA/prjtrellis">Project Trellis</a> for Lattice ECP5 FPGAs.
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</p>
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</div>
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<div class="diagram__diagram">
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<img src="assets/img/parts.svg" />
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</div>
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</div>
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<h3 class="diagram__header">
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Current status
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</h3>
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<div class="diagram__diagram">
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<div class="diagram__status">
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<div class="diagram__container">
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<table class="diagram__table">
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<thead>
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<tr>
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<td></td>
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<td>
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<a class="diagram__link" href="https://github.com/F4PGA/icestorm">
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Project Icestorm
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</a>
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</td>
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<td>
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<a class="diagram__link" href="https://github.com/F4PGA/prjtrellis">
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Project Trellis
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</a>
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</td>
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<td>
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<a class="diagram__link" href="https://github.com/F4PGA/prjxray">
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Project X-Ray
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</a>
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</td>
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<td>
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<a class="diagram__link" href="https://www.quicklogic.com/products/eos-s3/">
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QuickLogic Database
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</a>
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</td>
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</tr>
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</thead>
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<tbody>
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<tr>
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<td>
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Basic&nbsp;Tiles:
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<ul>
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<li>Logic</li>
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<li>Block&nbsp;RAM</li>
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</ul>
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</td>
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<!-- icestorm -->
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<td>
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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<!-- trellis -->
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<td>
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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<!-- x-ray -->
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<td>
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/partial.svg" alt="" />
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</td>
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<!-- quicklogic -->
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<td>
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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</tr>
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<tr>
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<td>
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Advanced&nbsp;Tiles:
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<ul>
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<li>DSP</li>
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<li>Hard&nbsp;Blocks</li>
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<li>Clock&nbsp;Tiles</li>
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<li>IO&nbsp;Tiles</li>
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</ul>
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</td>
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<!-- icestorm -->
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<td>
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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<!-- trellis -->
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<td>
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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<!-- x-ray -->
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<td>
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<img class="icon icon--large" src="assets/img/partial.svg" alt="" />
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<img class="icon icon--small" src="assets/img/cross.svg" alt="" />
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<img class="icon icon--small" src="assets/img/cross.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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<!-- quicklogic -->
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<td>
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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</tr>
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<tr>
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<td>
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Routing:
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<ul>
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<li>Logic</li>
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<li>Clock</li>
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</ul>
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</td>
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<td>
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<!-- icestorm -->
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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<!-- trellis -->
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<td>
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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<!-- x-ray -->
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<td>
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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<!-- quicklogic -->
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<td>
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<img class="icon icon--large" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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<img class="icon icon--small" src="assets/img/tick.svg" alt="" />
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</td>
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</tr>
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</tbody>
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</table>
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</div>
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</div>
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</div>
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</section>
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<section class="row subprojects" id="subprojects">
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<h2 class="row__header subprojects__header">
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<span class="underline"> Supported Architectures</span>
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</h2>
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<div class="subprojects__tiles">
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<div class="subproject__tile">
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<div class="subproject__details">
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<h4>Xilinx 7-Series </h4>
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<p class="subproject__description">
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The most popular Xilinx <br /> FPGA family
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</p>
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<a class="subproject__more inline-link" target="_blank"
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href="https://www.xilinx.com/video/fpga/7-series-fpga-overview.html">learn more</a>
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</div>
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</div>
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<div class="subproject__tile">
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<div class="subproject__details">
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<h4>Lattice ice40 </h4>
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<p class="subproject__description">
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World's smallest FPGAs <br /> for mobile devices
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</p>
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<a class="subproject__more inline-link" target="_blank"
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href="http://www.latticesemi.com/iCE40">learn more</a>
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</div>
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</div>
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<div class="subproject__tile">
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<div class="subproject__details">
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<h4>Lattice ecp5 </h4>
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<p class="subproject__description">
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Low cost FPGAs with <br /> high performance features
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</p>
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<a class="subproject__more inline-link" target="_blank"
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href="https://www.latticesemi.com/Products/FPGAandCPLD/ECP5">learn more</a>
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</div>
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</div>
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</div>
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<div class="subprojects__tiles">
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<div class="subproject__tile">
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<div class="subproject__details">
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<h4>QuickLogic EOS S3</h4>
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<p class="subproject__description">
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FPGA + CPU <br /> sensor processing platform
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</p>
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<a class="subproject__more inline-link" target="_blank"
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href="https://www.quicklogic.com/products/eos-s3/">learn more
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</a>
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</div>
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</div>
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<div class="subproject__tile">
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<div class="subproject__details">
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<h4>QuickLogic QLF K4N8</h4>
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<p class="subproject__description">
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A 24x24 eFPGA with <br /> 6144 flip-flops, 4608 LUT4s, <br /> adder and shift-register support
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</p>
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<a class="subproject__more inline-link" target="_blank"
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href="https://www.quicklogic.com/products/efpga/efpga-ip-software/">learn more
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</a>
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</div>
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</div>
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<div class="subproject__tile">
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<div class="subproject__details">
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<h4>Do you want to <br /> add more?</h4>
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<p class="subproject__description">Help us!</p>
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<a class="subproject__more inline-link" href="developers.html">learn more</a>
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</div>
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</div>
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</div>
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</section>
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<section class="row boards" id="boards">

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