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[RISCV] Change required features for Zvfhmin intrinsics from ZvfhminOrZvfh to Zvfhmin (llvm#77866)
From llvm#75735, Zvfh implies Zvfhmin.
1 parent e3fde34 commit 1e51b35

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4 files changed

+26
-27
lines changed

4 files changed

+26
-27
lines changed

‎clang/include/clang/Basic/riscv_vector.td‎

Lines changed: 22 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -117,7 +117,7 @@ multiclass RVVIndexedLoad<string op> {
117117
defvar eew = eew_list[0];
118118
defvar eew_type = eew_list[1];
119119
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
120-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
120+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
121121
[]<string>) in {
122122
def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>;
123123
if !not(IsFloat<type>.val) then {
@@ -128,7 +128,7 @@ multiclass RVVIndexedLoad<string op> {
128128
defvar eew64 = "64";
129129
defvar eew64_type = "(Log2EEW:6)";
130130
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
131-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
131+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
132132
["RV64"]) in {
133133
def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>;
134134
if !not(IsFloat<type>.val) then {
@@ -222,7 +222,7 @@ multiclass RVVIndexedStore<string op> {
222222
defvar eew = eew_list[0];
223223
defvar eew_type = eew_list[1];
224224
let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask",
225-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
225+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
226226
[]<string>) in {
227227
def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>;
228228
if !not(IsFloat<type>.val) then {
@@ -233,7 +233,7 @@ multiclass RVVIndexedStore<string op> {
233233
defvar eew64 = "64";
234234
defvar eew64_type = "(Log2EEW:6)";
235235
let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask",
236-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh", "RV64"],
236+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"],
237237
["RV64"]) in {
238238
def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>;
239239
if !not(IsFloat<type>.val) then {
@@ -681,30 +681,30 @@ let HasBuiltinAlias = false,
681681
def vlm: RVVVLEMaskBuiltin;
682682
defm vle8: RVVVLEBuiltin<["c"]>;
683683
defm vle16: RVVVLEBuiltin<["s"]>;
684-
let Name = "vle16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
684+
let Name = "vle16_v", RequiredFeatures = ["Zvfhmin"] in
685685
defm vle16_h: RVVVLEBuiltin<["x"]>;
686686
defm vle32: RVVVLEBuiltin<["i","f"]>;
687687
defm vle64: RVVVLEBuiltin<["l","d"]>;
688688

689689
def vsm : RVVVSEMaskBuiltin;
690690
defm vse8 : RVVVSEBuiltin<["c"]>;
691691
defm vse16: RVVVSEBuiltin<["s"]>;
692-
let Name = "vse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
692+
let Name = "vse16_v", RequiredFeatures = ["Zvfhmin"] in
693693
defm vse16_h: RVVVSEBuiltin<["x"]>;
694694
defm vse32: RVVVSEBuiltin<["i","f"]>;
695695
defm vse64: RVVVSEBuiltin<["l","d"]>;
696696

697697
// 7.5. Vector Strided Instructions
698698
defm vlse8: RVVVLSEBuiltin<["c"]>;
699699
defm vlse16: RVVVLSEBuiltin<["s"]>;
700-
let Name = "vlse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
700+
let Name = "vlse16_v", RequiredFeatures = ["Zvfhmin"] in
701701
defm vlse16_h: RVVVLSEBuiltin<["x"]>;
702702
defm vlse32: RVVVLSEBuiltin<["i","f"]>;
703703
defm vlse64: RVVVLSEBuiltin<["l","d"]>;
704704

705705
defm vsse8 : RVVVSSEBuiltin<["c"]>;
706706
defm vsse16: RVVVSSEBuiltin<["s"]>;
707-
let Name = "vsse16_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
707+
let Name = "vsse16_v", RequiredFeatures = ["Zvfhmin"] in
708708
defm vsse16_h: RVVVSSEBuiltin<["x"]>;
709709
defm vsse32: RVVVSSEBuiltin<["i","f"]>;
710710
defm vsse64: RVVVSSEBuiltin<["l","d"]>;
@@ -719,7 +719,7 @@ defm : RVVIndexedStore<"vsoxei">;
719719
// 7.7. Unit-stride Fault-Only-First Loads
720720
defm vle8ff: RVVVLEFFBuiltin<["c"]>;
721721
defm vle16ff: RVVVLEFFBuiltin<["s"]>;
722-
let Name = "vle16ff_v", RequiredFeatures = ["ZvfhminOrZvfh"] in
722+
let Name = "vle16ff_v", RequiredFeatures = ["Zvfhmin"] in
723723
defm vle16ff: RVVVLEFFBuiltin<["x"]>;
724724
defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>;
725725
defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>;
@@ -738,7 +738,7 @@ multiclass RVVUnitStridedSegLoadTuple<string op> {
738738
IRName = op # nf,
739739
MaskedIRName = op # nf # "_mask",
740740
NF = nf,
741-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
741+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
742742
[]<string>),
743743
ManualCodegen = [{
744744
{
@@ -800,7 +800,7 @@ multiclass RVVUnitStridedSegStoreTuple<string op> {
800800
MaskedIRName = op # nf # "_mask",
801801
NF = nf,
802802
HasMaskedOffOperand = false,
803-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
803+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
804804
[]<string>),
805805
ManualCodegen = [{
806806
{
@@ -852,7 +852,7 @@ multiclass RVVUnitStridedSegLoadFFTuple<string op> {
852852
IRName = op # nf # "ff",
853853
MaskedIRName = op # nf # "ff_mask",
854854
NF = nf,
855-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
855+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
856856
[]<string>),
857857
ManualCodegen = [{
858858
{
@@ -927,7 +927,7 @@ multiclass RVVStridedSegLoadTuple<string op> {
927927
IRName = op # nf,
928928
MaskedIRName = op # nf # "_mask",
929929
NF = nf,
930-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
930+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
931931
[]<string>),
932932
ManualCodegen = [{
933933
{
@@ -991,7 +991,7 @@ multiclass RVVStridedSegStoreTuple<string op> {
991991
NF = nf,
992992
HasMaskedOffOperand = false,
993993
MaskedPolicyScheme = NonePolicy,
994-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
994+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
995995
[]<string>),
996996
ManualCodegen = [{
997997
{
@@ -1040,7 +1040,7 @@ multiclass RVVIndexedSegLoadTuple<string op> {
10401040
IRName = op # nf,
10411041
MaskedIRName = op # nf # "_mask",
10421042
NF = nf,
1043-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
1043+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
10441044
[]<string>),
10451045
ManualCodegen = [{
10461046
{
@@ -1103,7 +1103,7 @@ multiclass RVVIndexedSegStoreTuple<string op> {
11031103
NF = nf,
11041104
HasMaskedOffOperand = false,
11051105
MaskedPolicyScheme = NonePolicy,
1106-
RequiredFeatures = !if(!eq(type, "x"), ["ZvfhminOrZvfh"],
1106+
RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"],
11071107
[]<string>),
11081108
ManualCodegen = [{
11091109
{
@@ -1345,7 +1345,7 @@ let HasMasked = false,
13451345
[["v", "Uv", "UvUv"]]>;
13461346
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "csilfd",
13471347
[["v", "v", "vv"]]>;
1348-
let RequiredFeatures = ["ZvfhminOrZvfh"] in
1348+
let RequiredFeatures = ["Zvfhmin"] in
13491349
defm vmv_v : RVVOutBuiltinSet<"vmv_v_v", "x",
13501350
[["v", "v", "vv"]]>;
13511351
let SupportOverloading = false in
@@ -1841,7 +1841,7 @@ let HasMasked = false,
18411841
}] in {
18421842
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "fd",
18431843
[["vvm", "v", "vvvm"]]>;
1844-
let RequiredFeatures = ["ZvfhminOrZvfh"] in
1844+
let RequiredFeatures = ["Zvfhmin"] in
18451845
defm vmerge : RVVOutOp1BuiltinSet<"vmerge", "x",
18461846
[["vvm", "v", "vvvm"]]>;
18471847
defm vfmerge : RVVOutOp1BuiltinSet<"vfmerge", "xfd",
@@ -1869,7 +1869,7 @@ let Log2LMUL = [-3, -2, -1, 0, 1, 2] in {
18691869
def vfwcvt_f_xu_v : RVVConvBuiltin<"Fw", "FwUv", "csi", "vfwcvt_f">;
18701870
def vfwcvt_f_x_v : RVVConvBuiltin<"Fw", "Fwv", "csi", "vfwcvt_f">;
18711871
def vfwcvt_f_f_v : RVVConvBuiltin<"w", "wv", "f", "vfwcvt_f">;
1872-
let RequiredFeatures = ["ZvfhminOrZvfh"] in
1872+
let RequiredFeatures = ["Zvfhmin"] in
18731873
def vfwcvt_f_f_v_fp16 : RVVConvBuiltin<"w", "wv", "x", "vfwcvt_f"> {
18741874
let Name = "vfwcvt_f_f_v";
18751875
let IRName = "vfwcvt_f_f_v";
@@ -1966,7 +1966,7 @@ let ManualCodegen = [{
19661966
}
19671967
let OverloadedName = "vfncvt_f" in {
19681968
defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vwu"]]>;
1969-
let RequiredFeatures = ["ZvfhminOrZvfh"] in
1969+
let RequiredFeatures = ["Zvfhmin"] in
19701970
defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vwu"]]>;
19711971
}
19721972
}
@@ -2011,7 +2011,7 @@ let ManualCodegen = [{
20112011
}
20122012
let OverloadedName = "vfncvt_f" in {
20132013
defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "f", [["v", "vw"]]>;
2014-
let RequiredFeatures = ["ZvfhminOrZvfh"] in
2014+
let RequiredFeatures = ["Zvfhmin"] in
20152015
defm : RVVConvBuiltinSet<"vfncvt_f_f_w", "x", [["v", "vw"]]>;
20162016
}
20172017
}
@@ -2271,7 +2271,7 @@ let HasMasked = false, HasVL = false, IRName = "" in {
22712271
def vreinterpret_u_f : RVVBuiltin<"FvUv", "UvFv", "il", "Uv">;
22722272
def vreinterpret_f_i : RVVBuiltin<"vFv", "Fvv", "il", "Fv">;
22732273
def vreinterpret_f_u : RVVBuiltin<"UvFv", "FvUv", "il", "Fv">;
2274-
let RequiredFeatures = ["ZvfhminOrZvfh"] in {
2274+
let RequiredFeatures = ["Zvfhmin"] in {
22752275
def vreinterpret_i_h : RVVBuiltin<"Fvv", "vFv", "s", "v">;
22762276
def vreinterpret_u_h : RVVBuiltin<"FvUv", "UvFv", "s", "Uv">;
22772277
def vreinterpret_h_i : RVVBuiltin<"vFv", "Fvv", "s", "Fv">;

‎clang/include/clang/Support/RISCVVIntrinsicUtils.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -488,7 +488,7 @@ class RVVIntrinsic {
488488
enum RVVRequire : uint32_t {
489489
RVV_REQ_None = 0,
490490
RVV_REQ_RV64 = 1 << 0,
491-
RVV_REQ_ZvfhminOrZvfh = 1 << 1,
491+
RVV_REQ_Zvfhmin = 1 << 1,
492492
RVV_REQ_Xsfvcp = 1 << 2,
493493
RVV_REQ_Xsfvfnrclipxfqf = 1 << 3,
494494
RVV_REQ_Xsfvfwmaccqqq = 1 << 4,

‎clang/lib/Sema/SemaRISCVVectorLookup.cpp‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -274,9 +274,8 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics(
274274
continue;
275275

276276
if (BaseType == BasicType::Float16) {
277-
if ((Record.RequiredExtensions & RVV_REQ_ZvfhminOrZvfh) ==
278-
RVV_REQ_ZvfhminOrZvfh) {
279-
if (!TI.hasFeature("zvfh") && !TI.hasFeature("zvfhmin"))
277+
if ((Record.RequiredExtensions & RVV_REQ_Zvfhmin) == RVV_REQ_Zvfhmin) {
278+
if (!TI.hasFeature("zvfhmin"))
280279
continue;
281280
} else if (!TI.hasFeature("zvfh")) {
282281
continue;

‎clang/utils/TableGen/RISCVVEmitter.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -656,7 +656,7 @@ void RVVEmitter::createRVVIntrinsics(
656656
RVVRequire RequireExt =
657657
StringSwitch<RVVRequire>(RequiredFeature)
658658
.Case("RV64", RVV_REQ_RV64)
659-
.Case("ZvfhminOrZvfh", RVV_REQ_ZvfhminOrZvfh)
659+
.Case("Zvfhmin", RVV_REQ_Zvfhmin)
660660
.Case("Xsfvcp", RVV_REQ_Xsfvcp)
661661
.Case("Xsfvfnrclipxfqf", RVV_REQ_Xsfvfnrclipxfqf)
662662
.Case("Xsfvfwmaccqqq", RVV_REQ_Xsfvfwmaccqqq)

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