Eliminate the inline assembly in folly::Instructions

Summary:
These were previously inline assembly to get GCC & Clang to inline them even when we weren't compiling with the required instruction set enabled, however these are now all included in the baseline instruction set we assume is present, so the intrinsics all get inlined properly.
Switching over to the intrinsics also has the added benefit of allowing compile time folding that isn't possible with the inline assembly. This is particularly noticable with the bextr instruction, as the inline assembly version was actually generating worse code :(

Reviewed By: Gownta

Differential Revision: D74504609

fbshipit-source-id: d1a9ceac8522bd68213c9ff3cdfdc8cfa2ff1537

Author: Orvid

folly/compression/Instructions.h

@@ -18,17 +18,17 @@
 
 #include <glog/logging.h>
 
-#ifdef _MSC_VER
-#include <immintrin.h>
-#endif
-
 #include <string_view>
 
 #include <folly/CpuId.h>
 #include <folly/Portability.h>
 #include <folly/lang/Assume.h>
 #include <folly/portability/Builtins.h>
 
+#if FOLLY_X64 || defined(__i386__)
+#include <immintrin.h>
+#endif
+
 namespace folly {
 namespace compression {
 namespace instructions {
@@ -93,15 +93,8 @@ struct Nehalem : public Default {
   }
 
   static FOLLY_ALWAYS_INLINE uint64_t popcount(uint64_t value) {
-// POPCNT is supported starting with Intel Nehalem, AMD K10.
-#if defined(__GNUC__)
-    // GCC and Clang won't inline the intrinsics.
-    uint64_t result;
-    asm("popcntq %1, %0" : "=r"(result) : "r"(value));
-    return result;
-#else
+    // POPCNT is supported starting with Intel Nehalem, AMD K10.
     return uint64_t(_mm_popcnt_u64(value));
-#endif
   }
 };
 
@@ -113,45 +106,18 @@ struct Haswell : public Nehalem {
   }
 
   static FOLLY_ALWAYS_INLINE uint64_t blsr(uint64_t value) {
-// BMI1 is supported starting with Intel Haswell, AMD Piledriver.
-// BLSR combines two instructions into one and reduces register pressure.
-#if defined(__GNUC__)
-    // GCC and Clang won't inline the intrinsics.
-    uint64_t result;
-    asm("blsrq %1, %0" : "=r"(result) : "r"(value));
-    return result;
-#else
+    // BMI1 is supported starting with Intel Haswell, AMD Piledriver.
+    // BLSR combines two instructions into one and reduces register pressure.
     return _blsr_u64(value);
-#endif
   }
 
   static FOLLY_ALWAYS_INLINE uint64_t
   bextr(uint64_t value, uint32_t start, uint32_t length) {
-#if defined(__GNUC__)
-    // GCC and Clang won't inline the intrinsics.
-    // Encode parameters in `pattern` where `pattern[0:7]` is `start` and
-    // `pattern[8:15]` is `length`.
-    // Ref: Intel Advanced Vector Extensions Programming Reference
-    uint64_t pattern = start & 0xFF;
-    pattern = pattern | ((length & 0xFF) << 8);
-    uint64_t result;
-    asm("bextrq %2, %1, %0" : "=r"(result) : "r"(value), "r"(pattern));
-    return result;
-#else
     return _bextr_u64(value, start, length);
-#endif
   }
 
   static FOLLY_ALWAYS_INLINE uint64_t bzhi(uint64_t value, uint32_t index) {
-#if defined(__GNUC__)
-    // GCC and Clang won't inline the intrinsics.
-    const uint64_t index64 = index;
-    uint64_t result;
-    asm("bzhiq %2, %1, %0" : "=r"(result) : "r"(value), "r"(index64));
-    return result;
-#else
     return _bzhi_u64(value, index);
-#endif
   }
 };
 #endif