Commit 0cb53c1
[AMD] Implement
Similar to `tl.extra.cuda.globaltimer`, this PR exposes
`tl.extra.hip.memrealtime` for AMD GPU. This is useful
for measuring the timing information for AMD kernels.
Reference:
https://www.amd.com/content/dam/amd/en/documents/radeon-tech-docs/instruction-set-architectures/rdna2-shader-instruction-set-architecture.pdf
> 7.2.3. S_MEMREALTIME
> This instruction reads a 64-bit "real time-counter" and returns the
> value into a pair of SGPRS:
> SDST and SDST+1. The time value is from a clock for which the
> frequency is constant (not affected by power modes or core clock
> frequency changes).
> Because the instructions can return out-of-order, the only sensible
> way to use this counter is to implement S_WAITCNT 0; this imposes
> a wait for all data to return from previous SMEMs before continuing.tl.extra.hip.memrealtime for timing (#7282)1 parent 3317bae commit 0cb53c1
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