We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 7a4f4ce commit 6aee326Copy full SHA for 6aee326
L1Trigger/Configuration/python/customiseReEmul.py
@@ -261,6 +261,14 @@ def L1TReEmulMCFromRAW(process):
261
L1TReEmulFromRAW(process)
262
stage2L1Trigger.toModify(process.simEmtfDigis, CSCInput = 'simCscTriggerPrimitiveDigis:MPCSORTED')
263
stage2L1Trigger.toModify(process.simOmtfDigis, srcCSC = 'simCscTriggerPrimitiveDigis:MPCSORTED')
264
+
265
+ # Temporary fix for OMTF inputs in MC re-emulation
266
+ run3_GEM.toModify(process.simOmtfDigis,
267
+ srcRPC = 'muonRPCDigis',
268
+ srcDTPh = 'bmtfDigis',
269
+ srcDTTh = 'bmtfDigis'
270
+ )
271
272
return process
273
274
def L1TReEmulMCFromRAWSimEcalTP(process):
0 commit comments