oneAPI BSP support.

Author: haoyanwa

hls4ml/backends/oneapi/oneapi_backend.py

@@ -153,9 +153,9 @@ def create_initial_config(self, part='Arria10', clock_period=5, io_type='io_para
             # TODO:  add namespace
             'WriteTar': write_tar,
         }
-
-        if 'use_bsp' in _:
-            config['IS_BSP'] = True
+        # Target oneAPI Board Support Package (BSP).
+        if "use_oneapi_bsp" in _:
+            config['UseOneAPIBSP'] = _["use_oneapi_bsp"]
 
         return config
 

hls4ml/templates/oneapi/CMakeLists.txt

@@ -39,15 +39,19 @@ set(LIBRARY_NAME myproject-${LIB_STAMP})
 # specific part number (E.g. "10AS066N3F40E2SG") to generate a standalone IP.
 if(NOT DEFINED FPGA_DEVICE)
     set(FPGA_DEVICE "Agilex7")
+    set(BSP_FLAG "")
 endif()
 
+# Set the target to a BSP if we target an actual accelerator board.
+# hls-fpga-machine-learning insert oneapi_bsp_cmake_flag
+
 # Use cmake -DUSER_FPGA_FLAGS=<flags> to set extra flags for FPGA backend
 # compilation.
 # -Xsoptimize=latency Turns off the hyper-optimized handshake
 set(USER_FPGA_FLAGS -Wno-unused-label;${USER_FPGA_FLAGS};-Xsoptimize=latency)
 
 # Use cmake -DUSER_FLAGS=<flags> to set extra flags for general compilation.
-set(USER_FLAGS -Wno-unused-label -fconstexpr-steps=134217728 ${USER_FLAGS})
+set(USER_FLAGS -Wno-unused-label -fconstexpr-steps=134217728 ${USER_FLAGS} ${BSP_FLAG})
 
 # Use cmake -DUSER_INCLUDE_PATHS=<paths> to set extra paths for general
 # compilation.

hls4ml/templates/oneapi/firmware/myproject.h

@@ -11,7 +11,7 @@ using PipeProps = decltype(sycl::ext::oneapi::experimental::properties(sycl::ext
 // Pipe properties for host pipes. Host pipes connect to the data source DMA and sink DMA.
 // They are connected to the first and the last layer to stream data into and out from the kernel.
 using HostPipePropertiesT = decltype(sycl::ext::oneapi::experimental::properties(
-    sycl::ext::intel::experimental::ready_latency<0>, sycl::ext::intel::experimental::bits_per_symbol<8>,
+    sycl::ext::intel::experimental::ready_latency<0>, sycl::ext::intel::experimental::bits_per_symbol<16>,
     sycl::ext::intel::experimental::uses_valid<true>, sycl::ext::intel::experimental::first_symbol_in_high_order_bits<true>,
     sycl::ext::intel::experimental::protocol_avalon_streaming_uses_ready));
 
@@ -127,12 +127,15 @@ template <class src_pipe, class dst_T> struct DMA_convert_data_back {
 class MyProjectID;
 
 struct MyProject {
-
+#ifndef IS_BSP
     // kernel property method to config invocation interface
     auto get(sycl::ext::oneapi::experimental::properties_tag) {
         return sycl::ext::oneapi::experimental::properties{sycl::ext::intel::experimental::streaming_interface<>,
                                                            sycl::ext::intel::experimental::pipelined<>};
     }
+#else
+    // kernel properties and pipelining is not supported in BSP.
+#endif
 
     SYCL_EXTERNAL void operator()() const;
 };

hls4ml/writer/oneapi_writer.py

@@ -557,6 +557,10 @@ def write_build_script(self, model):
                 if 'set(FPGA_DEVICE' in line:
                     line = f'    set(FPGA_DEVICE "{device}")\n'
 
+                if model.config.get_config_value('UseOneAPIBSP'):
+                    if 'hls-fpga-machine-learning insert oneapi_bsp_cmake_flag' in line:
+                        line = f'set(BSP_FLAG "-DIS_BSP")'
+
                 fout.write(line)
 
     def write_nnet_utils(self, model):