|
1 | 1 | import glob |
2 | 2 | import os |
| 3 | +import stat |
3 | 4 | import tarfile |
4 | 5 | from collections import OrderedDict |
| 6 | +from pathlib import Path |
5 | 7 | from shutil import copyfile, copytree, rmtree |
6 | 8 |
|
7 | 9 | import numpy as np |
@@ -749,55 +751,50 @@ def write_build_script(self, model): |
749 | 751 | model (ModelGraph): the hls4ml model. |
750 | 752 | """ |
751 | 753 |
|
752 | | - filedir = os.path.dirname(os.path.abspath(__file__)) |
| 754 | + filedir = Path(__file__).parent |
753 | 755 |
|
754 | 756 | # build_prj.tcl |
755 | | - srcpath = os.path.join(filedir, '../templates/catapult/build_prj.tcl') |
756 | | - dstpath = f'{model.config.get_output_dir()}/build_prj.tcl' |
757 | | - # copyfile(srcpath, dstpath) |
758 | | - f = open(srcpath) |
759 | | - fout = open(dstpath, 'w') |
760 | | - for line in f.readlines(): |
761 | | - indent = line[: len(line) - len(line.lstrip())] |
762 | | - line = line.replace('myproject', model.config.get_project_name()) |
763 | | - line = line.replace('CATAPULT_DIR', model.config.get_project_dir()) |
764 | | - if '#hls-fpga-machine-learning insert techlibs' in line: |
765 | | - if model.config.get_config_value('Technology') is None: |
766 | | - if model.config.get_config_value('Part') is not None: |
767 | | - line = indent + 'setup_xilinx_part {{{}}}\n'.format(model.config.get_config_value('Part')) |
768 | | - elif model.config.get_config_value('ASICLibs') is not None: |
769 | | - line = indent + 'setup_asic_libs {{{}}}\n'.format(model.config.get_config_value('ASICLibs')) |
770 | | - else: |
771 | | - if model.config.get_config_value('Technology') == 'asic': |
772 | | - line = indent + 'setup_asic_libs {{{}}}\n'.format(model.config.get_config_value('ASICLibs')) |
| 757 | + srcpath = (filedir / '../templates/catapult/build_prj.tcl').resolve() |
| 758 | + dstpath = Path(f'{model.config.get_output_dir()}/build_prj.tcl').resolve() |
| 759 | + with open(srcpath) as src, open(dstpath, 'w') as dst: |
| 760 | + for line in src.readlines(): |
| 761 | + indent = line[: len(line) - len(line.lstrip())] |
| 762 | + line = line.replace('myproject', model.config.get_project_name()) |
| 763 | + line = line.replace('CATAPULT_DIR', model.config.get_project_dir()) |
| 764 | + if '#hls-fpga-machine-learning insert techlibs' in line: |
| 765 | + if model.config.get_config_value('Technology') is None: |
| 766 | + if model.config.get_config_value('Part') is not None: |
| 767 | + line = indent + 'setup_xilinx_part {{{}}}\n'.format(model.config.get_config_value('Part')) |
| 768 | + elif model.config.get_config_value('ASICLibs') is not None: |
| 769 | + line = indent + 'setup_asic_libs {{{}}}\n'.format(model.config.get_config_value('ASICLibs')) |
773 | 770 | else: |
774 | | - line = indent + 'setup_xilinx_part {{{}}}\n'.format(model.config.get_config_value('Part')) |
775 | | - elif '#hls-fpga-machine-learning insert invoke_args' in line: |
776 | | - tb_in_file = model.config.get_config_value('InputData') |
777 | | - tb_out_file = model.config.get_config_value('OutputPredictions') |
778 | | - invoke_args = '$sfd/firmware/weights' |
779 | | - if tb_in_file is not None: |
780 | | - invoke_args = invoke_args + f' $sfd/tb_data/{tb_in_file}' |
781 | | - if tb_out_file is not None: |
782 | | - invoke_args = invoke_args + f' $sfd/tb_data/{tb_out_file}' |
783 | | - line = indent + f'flow package option set /SCVerify/INVOKE_ARGS "{invoke_args}"\n' |
784 | | - elif 'set hls_clock_period 5' in line: |
785 | | - line = indent + 'set hls_clock_period {}\n'.format(model.config.get_config_value('ClockPeriod')) |
786 | | - fout.write(line) |
787 | | - f.close() |
788 | | - fout.close() |
| 771 | + if model.config.get_config_value('Technology') == 'asic': |
| 772 | + line = indent + 'setup_asic_libs {{{}}}\n'.format(model.config.get_config_value('ASICLibs')) |
| 773 | + else: |
| 774 | + line = indent + 'setup_xilinx_part {{{}}}\n'.format(model.config.get_config_value('Part')) |
| 775 | + elif '#hls-fpga-machine-learning insert invoke_args' in line: |
| 776 | + tb_in_file = model.config.get_config_value('InputData') |
| 777 | + tb_out_file = model.config.get_config_value('OutputPredictions') |
| 778 | + invoke_args = '$sfd/firmware/weights' |
| 779 | + if tb_in_file is not None: |
| 780 | + invoke_args = invoke_args + f' $sfd/tb_data/{tb_in_file}' |
| 781 | + if tb_out_file is not None: |
| 782 | + invoke_args = invoke_args + f' $sfd/tb_data/{tb_out_file}' |
| 783 | + line = indent + f'flow package option set /SCVerify/INVOKE_ARGS "{invoke_args}"\n' |
| 784 | + elif 'set hls_clock_period 5' in line: |
| 785 | + line = indent + 'set hls_clock_period {}\n'.format(model.config.get_config_value('ClockPeriod')) |
| 786 | + dst.write(line) |
789 | 787 |
|
790 | 788 | # build_lib.sh |
791 | | - f = open(os.path.join(filedir, '../templates/catapult/build_lib.sh')) |
792 | | - fout = open(f'{model.config.get_output_dir()}/build_lib.sh', 'w') |
793 | | - |
794 | | - for line in f.readlines(): |
795 | | - line = line.replace('myproject', model.config.get_project_name()) |
796 | | - line = line.replace('mystamp', model.config.get_config_value('Stamp')) |
797 | | - |
798 | | - fout.write(line) |
799 | | - f.close() |
800 | | - fout.close() |
| 789 | + build_lib_src = (filedir / '../templates/catapult/build_lib.sh').resolve() |
| 790 | + build_lib_dst = Path(f'{model.config.get_output_dir()}/build_lib.sh').resolve() |
| 791 | + with open(build_lib_src) as src, open(build_lib_dst, 'w') as dst: |
| 792 | + for line in src.readlines(): |
| 793 | + line = line.replace('myproject', model.config.get_project_name()) |
| 794 | + line = line.replace('mystamp', model.config.get_config_value('Stamp')) |
| 795 | + |
| 796 | + dst.write(line) |
| 797 | + build_lib_dst.chmod(build_lib_dst.stat().st_mode | stat.S_IEXEC) |
801 | 798 |
|
802 | 799 | def write_nnet_utils(self, model): |
803 | 800 | """Copy the nnet_utils, AP types headers and any custom source to the project output directory |
|
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