@@ -114,9 +114,11 @@ def write_project_cpp(self, model):
114114 ## myproject.cpp
115115 ###################
116116
117+ project_name = model .config .get_project_name ()
118+
117119 filedir = os .path .dirname (os .path .abspath (__file__ ))
118120 f = open (os .path .join (filedir , '../templates/quartus/firmware/myproject.cpp' ), 'r' )
119- fout = open ('{}/firmware/{}.cpp' .format (model .config .get_output_dir (), model . config . get_project_name () ), 'w' )
121+ fout = open ('{}/firmware/{}.cpp' .format (model .config .get_output_dir (), project_name ), 'w' )
120122
121123 model_inputs = model .get_input_variables ()
122124 model_outputs = model .get_output_variables ()
@@ -127,7 +129,7 @@ def write_project_cpp(self, model):
127129 for line in f .readlines ():
128130 # Add headers to weights and biases
129131 if 'myproject' in line :
130- newline = line .replace ('myproject' , model . config . get_project_name () )
132+ newline = line .replace ('myproject' , project_name )
131133
132134 # Intel HLS 'streams' need to be passed by reference to top-level entity or declared as global variables
133135 # Streams cannot be declared inside a function
@@ -146,29 +148,29 @@ def write_project_cpp(self, model):
146148 elif '//hls-fpga-machine-learning instantiate GCC top-level' in line :
147149 newline = line
148150 if io_type == 'io_stream' :
149- newline += 'void myproject (\n '
151+ newline += f 'void { project_name } (\n '
150152 for inp in model_inputs :
151153 newline += indent + 'stream_in<{}> &{}_stream,\n ' .format (inp .type .name , inp .name )
152154 for out in model_outputs :
153155 newline += indent + 'stream_out<{}> &{}_stream\n ' .format (out .type .name , out .name )
154156 newline += ') {\n '
155157 if io_type == 'io_parallel' :
156- newline = 'output_data myproject (\n '
158+ newline = f 'output_data { project_name } (\n '
157159 newline += indent + 'input_data inputs\n '
158160 newline += ') {\n '
159161
160162 # Instantiate HLS top-level function, to be used during HLS synthesis
161163 elif '//hls-fpga-machine-learning instantiate HLS top-level' in line :
162164 newline = line
163165 if io_type == 'io_stream' :
164- newline += 'component void myproject (\n '
166+ newline += f 'component void { project_name } (\n '
165167 for inp in model_inputs :
166168 newline += indent + 'stream_in<{}> &{}_stream,\n ' .format (inp .type .name , inp .name )
167169 for out in model_outputs :
168170 newline += indent + 'stream_out<{}> &{}_stream\n ' .format (out .type .name , out .name )
169171 newline += ') {\n '
170172 if io_type == 'io_parallel' :
171- newline += 'component output_data myproject (\n '
173+ newline += f 'component output_data { project_name } (\n '
172174 newline += indent + 'input_data inputs\n '
173175 newline += ') {\n '
174176
@@ -263,9 +265,11 @@ def write_project_header(self, model):
263265 ## myproject.h
264266 #######################
265267
268+ project_name = model .config .get_project_name ()
269+
266270 filedir = os .path .dirname (os .path .abspath (__file__ ))
267271 f = open (os .path .join (filedir , '../templates/quartus/firmware/myproject.h' ), 'r' )
268- fout = open ('{}/firmware/{}.h' .format (model .config .get_output_dir (), model . config . get_project_name () ), 'w' )
272+ fout = open ('{}/firmware/{}.h' .format (model .config .get_output_dir (), project_name ), 'w' )
269273
270274 model_inputs = model .get_input_variables ()
271275 model_outputs = model .get_output_variables ()
@@ -276,39 +280,40 @@ def write_project_header(self, model):
276280
277281 for line in f .readlines ():
278282 if 'MYPROJECT' in line :
279- newline = line .replace ('MYPROJECT' , format (model . config . get_project_name () .upper ()))
283+ newline = line .replace ('MYPROJECT' , format (project_name .upper ()))
280284
281285 elif 'myproject' in line :
282- newline = line .replace ('myproject' , model . config . get_project_name () )
286+ newline = line .replace ('myproject' , project_name )
283287
284288 elif '//hls-fpga-machine-learning instantiate GCC top-level' in line :
285289 newline = line
286290 # For io_stream, input and output are passed by reference; see myproject.h & myproject.cpp for more details
291+
287292 if io_type == 'io_stream' :
288- newline += 'void myproject (\n '
293+ newline += f 'void { project_name } (\n '
289294 for inp in model_inputs :
290295 newline += indent + 'stream_in<{}> &{}_stream,\n ' .format (inp .type .name , inp .name )
291296 for out in model_outputs :
292297 newline += indent + 'stream_out<{}> &{}_stream\n ' .format (out .type .name , out .name )
293298 newline += ');\n '
294299 # In io_parallel, a struct is returned; see myproject.h & myproject.cpp for more details
295300 else :
296- newline += 'output_data myproject (\n '
301+ newline += f 'output_data { project_name } (\n '
297302 newline += indent + 'input_data inputs\n '
298303 newline += ');\n '
299304
300305 # Similar to GCC instantiation, but with the keyword 'component'
301306 elif '//hls-fpga-machine-learning instantiate HLS top-level' in line :
302307 newline = line
303308 if io_type == 'io_stream' :
304- newline += 'component void myproject (\n '
309+ newline += f 'component void { project_name } (\n '
305310 for inp in model_inputs :
306311 newline += indent + 'stream_in<{}> &{}_stream,\n ' .format (inp .type .name , inp .name )
307312 for out in model_outputs :
308313 newline += indent + 'stream_out<{}> &{}_stream\n ' .format (out .type .name , out .name )
309314 newline += ');\n '
310315 else :
311- newline += 'component output_data myproject (\n '
316+ newline += f 'component output_data { project_name } (\n '
312317 newline += indent + 'input_data inputs\n '
313318 newline += ');\n '
314319
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