@@ -147,10 +147,10 @@ def write_kernel(self, model):
147147 for line in f_source .readlines ():
148148 if "myproject" in line :
149149 newline = line .replace ("myproject" , format (model .config .get_project_name ()))
150- elif "/*IN_HW_QUANT*/" in line :
151- newline = line .replace ("/*IN_HW_QUANT*/" , "(in_buffer_t)" if isHwQuant else "" )
152- elif "/*OUT_HW_QUANT*/" in line :
153- newline = line .replace ("/*OUT_HW_QUANT*/" , "(float)" if isHwQuant else "" )
150+ elif "/*IN_HW_QUANT*/ " in line :
151+ newline = line .replace ("/*IN_HW_QUANT*/ " , "(in_buffer_t)" if isHwQuant else "" )
152+ elif "/*OUT_HW_QUANT*/ " in line :
153+ newline = line .replace ("/*OUT_HW_QUANT*/ " , "(float)" if isHwQuant else "" )
154154 else :
155155 newline = line
156156
@@ -188,10 +188,10 @@ def write_host(self, model):
188188 + dataType
189189 + " fpga(BATCHSIZE * INSTREAMSIZE, BATCHSIZE * OUTSTREAMSIZE, NUM_CU, NUM_THREAD, 10);"
190190 )
191- elif "/*IN_TYPE_CAST*/" in line :
192- newline = line .replace ("/*IN_TYPE_CAST*/" , "" if isHwQuant else "(in_buffer_t)" )
193- elif "/*OUT_TYPE_CAST*/" in line :
194- newline = line .replace ("/*OUT_TYPE_CAST*/" , "" if isHwQuant else "(float)" )
191+ elif "/*IN_TYPE_CAST*/ " in line :
192+ newline = line .replace ("/*IN_TYPE_CAST*/ " , "" if isHwQuant else "(in_buffer_t)" )
193+ elif "/*OUT_TYPE_CAST*/ " in line :
194+ newline = line .replace ("/*OUT_TYPE_CAST*/ " , "" if isHwQuant else "(float)" )
195195 else :
196196 newline = line
197197
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