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jmduartejmduarte
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restore build_prj.tcl
1 parent c1ea360 commit 7933d42

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‎hls4ml/templates/vivado/build_prj.tcl‎

Lines changed: 125 additions & 127 deletions
Original file line numberDiff line numberDiff line change
@@ -2,14 +2,14 @@
22
# HLS4ML
33
#################
44
array set opt {
5-
reset 0
6-
csim 1
7-
synth 1
8-
cosim 1
9-
validation 1
10-
export 0
11-
vsynth 0
12-
fifo_opt 0
5+
reset 0
6+
csim 1
7+
synth 1
8+
cosim 1
9+
validation 1
10+
export 0
11+
vsynth 0
12+
fifo_opt 0
1313
}
1414

1515
set tcldir [file dirname [info script]]
@@ -19,7 +19,7 @@ proc remove_recursive_log_wave {} {
1919
set tcldir [file dirname [info script]]
2020
source [file join $tcldir project.tcl]
2121

22-
set filename ${myproject}_prj/solution1/sim/verilog/${myproject}.tcl
22+
set filename ${project_name}_prj/solution1/sim/verilog/${project_name}.tcl
2323
set timestamp [clock format [clock seconds] -format {%Y%m%d%H%M%S}]
2424
set temp $filename.new.$timestamp
2525
# set backup $filename.bak.$timestamp
@@ -35,19 +35,19 @@ proc remove_recursive_log_wave {} {
3535
puts $out $line
3636
}
3737

38-
close $in
39-
close $out
38+
close $in
39+
close $out
4040

41-
# move the new data to the proper filename
42-
file delete -force $filename
43-
file rename -force $temp $filename
41+
# move the new data to the proper filename
42+
file delete -force $filename
43+
file rename -force $temp $filename
4444
}
4545

4646
proc add_vcd_instructions_tcl {} {
4747
set tcldir [file dirname [info script]]
4848
source [file join $tcldir project.tcl]
4949

50-
set filename ${myproject}_prj/solution1/sim/verilog/${myproject}.tcl
50+
set filename ${project_name}_prj/solution1/sim/verilog/${project_name}.tcl
5151
set timestamp [clock format [clock seconds] -format {%Y%m%d%H%M%S}]
5252
set temp $filename.new.$timestamp
5353
# set backup $filename.bak.$timestamp
@@ -58,45 +58,43 @@ proc add_vcd_instructions_tcl {} {
5858
# line-by-line, read the original file
5959
while {[gets $in line] != -1} {
6060
if {[string equal "$line" "log_wave -r /"]} {
61-
set line {source "../../../../project.tcl"
62-
if {[string equal "$backend" "vivadoaccelerator"]} {
63-
current_scope [get_scopes -regex /apatb_${myproject}_axi_top/AESL_inst_${myproject}_axi/${myproject}_U0.*]
64-
set scopes [get_scopes -regexp {layer(\d*)_.*data_0_V_U.*}]
65-
append scopes { }
66-
current_scope /apatb_${myproject}_axi_top/AESL_inst_${myproject}_axi
67-
append scopes [get_scopes -regexp {(in_local_V_data.*_0_.*)}]
68-
append scopes { }
69-
append scopes [get_scopes -regexp {(out_local_V_data.*_0_.*)}]
70-
} else {
71-
current_scope [get_scopes -regex /apatb_${myproject}_top/AESL_inst_${myproject}]
72-
set scopes [get_scopes -regexp {layer(\d*)_.*data_0_V_U.*}]
73-
}
74-
open_vcd fifo_opt.vcd
75-
foreach scope $scopes {
76-
current_scope $scope
77-
if {[catch [get_objects usedw]] == 0} {
78-
puts "$scope skipped"
79-
continue
80-
}
81-
set usedw [get_objects usedw]
82-
set depth [get_objects DEPTH]
83-
add_wave $usedw
84-
log_vcd $usedw
85-
log_wave $usedw
86-
add_wave $depth
87-
log_vcd $depth
88-
log_wave $depth
89-
}
90-
}
91-
92-
set line [string map [list "myproject" $myproject] $line]
61+
set line {source "../../../../project.tcl"
62+
if {[string equal "$backend" "vivadoaccelerator"]} {
63+
current_scope [get_scopes -regex "/apatb_${project_name}_axi_top/AESL_inst_${project_name}_axi/${project_name}_U0.*"]
64+
set scopes [get_scopes -regexp {layer(\d*)_.*data_0_V_U.*}]
65+
append scopes { }
66+
current_scope "/apatb_${project_name}_axi_top/AESL_inst_${project_name}_axi"
67+
append scopes [get_scopes -regexp {(in_local_V_data.*_0_.*)}]
68+
append scopes { }
69+
append scopes [get_scopes -regexp {(out_local_V_data.*_0_.*)}]
70+
} else {
71+
current_scope [get_scopes -regex "/apatb_${project_name}_top/AESL_inst_${project_name}"]
72+
set scopes [get_scopes -regexp {layer(\d*)_.*data_0_V_U.*}]
73+
}
74+
open_vcd fifo_opt.vcd
75+
foreach scope $scopes {
76+
current_scope $scope
77+
if {[catch [get_objects usedw]] == 0} {
78+
puts "$scope skipped"
79+
continue
80+
}
81+
set usedw [get_objects usedw]
82+
set depth [get_objects DEPTH]
83+
add_wave $usedw
84+
log_vcd $usedw
85+
log_wave $usedw
86+
add_wave $depth
87+
log_vcd $depth
88+
log_wave $depth
89+
}
90+
}
9391
}
9492

9593
if {[string equal "$line" "quit"]} {
9694
set line {flush_vcd
97-
close_vcd
98-
quit
99-
}
95+
close_vcd
96+
quit
97+
}
10098
}
10199
# then write the transformed line
102100
puts $out $line
@@ -111,17 +109,17 @@ quit
111109
}
112110

113111
foreach arg $::argv {
114-
foreach o [lsort [array names opt]] {
115-
regexp "$o=+(\\w+)" $arg unused opt($o)
116-
}
112+
foreach o [lsort [array names opt]] {
113+
regexp "$o=+(\\w+)" $arg unused opt($o)
114+
}
117115
}
118116

119117
proc report_time { op_name time_start time_end } {
120-
set time_taken [expr $time_end - $time_start]
121-
set time_s [expr ($time_taken / 1000) % 60]
122-
set time_m [expr ($time_taken / (1000*60)) % 60]
123-
set time_h [expr ($time_taken / (1000*60*60)) % 24]
124-
puts "***** ${op_name} COMPLETED IN ${time_h}h${time_m}m${time_s}s *****"
118+
set time_taken [expr $time_end - $time_start]
119+
set time_s [expr ($time_taken / 1000) % 60]
120+
set time_m [expr ($time_taken / (1000*60)) % 60]
121+
set time_h [expr ($time_taken / (1000*60*60)) % 24]
122+
puts "***** ${op_name} COMPLETED IN ${time_h}h${time_m}m${time_s}s *****"
125123
}
126124

127125
# Compare file content: 1 = same, 0 = different
@@ -149,102 +147,102 @@ set CSIM_RESULTS "./tb_data/csim_results.log"
149147
set RTL_COSIM_RESULTS "./tb_data/rtl_cosim_results.log"
150148

151149
if {$opt(reset)} {
152-
open_project -reset ${myproject}_prj
150+
open_project -reset ${project_name}_prj
153151
} else {
154-
open_project ${myproject}_prj
152+
open_project ${project_name}_prj
155153
}
156-
set_top myproject
157-
add_files firmware/myproject.cpp -cflags "-std=c++0x"
158-
add_files -tb myproject_test.cpp -cflags "-std=c++0x"
154+
set_top ${project_name}
155+
add_files firmware/${project_name}.cpp -cflags "-std=c++0x"
156+
add_files -tb ${project_name}_test.cpp -cflags "-std=c++0x"
159157
add_files -tb firmware/weights
160158
add_files -tb tb_data
161159
if {$opt(reset)} {
162-
open_solution -reset "solution1"
160+
open_solution -reset "solution1"
163161
} else {
164-
open_solution "solution1"
162+
open_solution "solution1"
165163
}
166164
catch {config_array_partition -maximum_size 4096}
167165
config_compile -name_max_length 60
168-
set_part {xcku115-flvb2104-2-i}
169-
create_clock -period 5 -name default
166+
set_part $part
167+
create_clock -period $clock_period -name default
170168

171169

172170
if {$opt(csim)} {
173-
puts "***** C SIMULATION *****"
174-
set time_start [clock clicks -milliseconds]
175-
csim_design
176-
set time_end [clock clicks -milliseconds]
177-
report_time "C SIMULATION" $time_start $time_end
171+
puts "***** C SIMULATION *****"
172+
set time_start [clock clicks -milliseconds]
173+
csim_design
174+
set time_end [clock clicks -milliseconds]
175+
report_time "C SIMULATION" $time_start $time_end
178176
}
179177

180178
if {$opt(synth)} {
181-
puts "***** C/RTL SYNTHESIS *****"
182-
set time_start [clock clicks -milliseconds]
183-
csynth_design
184-
set time_end [clock clicks -milliseconds]
185-
report_time "C/RTL SYNTHESIS" $time_start $time_end
179+
puts "***** C/RTL SYNTHESIS *****"
180+
set time_start [clock clicks -milliseconds]
181+
csynth_design
182+
set time_end [clock clicks -milliseconds]
183+
report_time "C/RTL SYNTHESIS" $time_start $time_end
186184
}
187185

188186
if {$opt(cosim)} {
189-
puts "***** C/RTL SIMULATION *****"
190-
# TODO: This is a workaround (Xilinx defines __RTL_SIMULATION__ only for SystemC testbenches).
191-
add_files -tb myproject_test.cpp -cflags "-std=c++0x -DRTL_SIM"
192-
set time_start [clock clicks -milliseconds]
193-
194-
cosim_design -trace_level all -setup
195-
196-
if {$opt(fifo_opt)} {
197-
puts "\[hls4ml\] - FIFO optimization started"
198-
add_vcd_instructions_tcl
199-
}
200-
201-
remove_recursive_log_wave
202-
set old_pwd [pwd]
203-
cd ${myproject}_prj/solution1/sim/verilog/
204-
source run_sim.tcl
205-
cd $old_pwd
206-
207-
set time_end [clock clicks -milliseconds]
208-
puts "INFO:"
209-
if {[string equal "$backend" "vivadoaccelerator"]} {
210-
puts [read [open ${myproject}_prj/solution1/sim/report/${myproject}_axi_cosim.rpt r]]
211-
} else {
212-
puts [read [open ${myproject}_prj/solution1/sim/report/${myproject}_cosim.rpt r]]
213-
}
214-
report_time "C/RTL SIMULATION" $time_start $time_end
187+
puts "***** C/RTL SIMULATION *****"
188+
# TODO: This is a workaround (Xilinx defines __RTL_SIMULATION__ only for SystemC testbenches).
189+
add_files -tb ${project_name}_test.cpp -cflags "-std=c++0x -DRTL_SIM"
190+
set time_start [clock clicks -milliseconds]
191+
192+
cosim_design -trace_level all -setup
193+
194+
if {$opt(fifo_opt)} {
195+
puts "\[hls4ml\] - FIFO optimization started"
196+
add_vcd_instructions_tcl
197+
}
198+
199+
remove_recursive_log_wave
200+
set old_pwd [pwd]
201+
cd ${project_name}_prj/solution1/sim/verilog/
202+
source run_sim.tcl
203+
cd $old_pwd
204+
205+
set time_end [clock clicks -milliseconds]
206+
puts "INFO:"
207+
if {[string equal "$backend" "vivadoaccelerator"]} {
208+
puts [read [open ${project_name}_prj/solution1/sim/report/${project_name}_axi_cosim.rpt r]]
209+
} else {
210+
puts [read [open ${project_name}_prj/solution1/sim/report/${project_name}_cosim.rpt r]]
211+
}
212+
report_time "C/RTL SIMULATION" $time_start $time_end
215213
}
216214

217215
if {$opt(validation)} {
218-
puts "***** C/RTL VALIDATION *****"
219-
if {[compare_files $CSIM_RESULTS $RTL_COSIM_RESULTS]} {
220-
puts "INFO: Test PASSED"
221-
} else {
222-
puts "ERROR: Test failed"
223-
puts "ERROR: - csim log: $CSIM_RESULTS"
224-
puts "ERROR: - RTL-cosim log: $RTL_COSIM_RESULTS"
225-
exit 1
226-
}
216+
puts "***** C/RTL VALIDATION *****"
217+
if {[compare_files $CSIM_RESULTS $RTL_COSIM_RESULTS]} {
218+
puts "INFO: Test PASSED"
219+
} else {
220+
puts "ERROR: Test failed"
221+
puts "ERROR: - csim log: $CSIM_RESULTS"
222+
puts "ERROR: - RTL-cosim log: $RTL_COSIM_RESULTS"
223+
exit 1
224+
}
227225
}
228226

229227
if {$opt(export)} {
230-
puts "***** EXPORT IP *****"
231-
set time_start [clock clicks -milliseconds]
232-
export_design -format ip_catalog
233-
set time_end [clock clicks -milliseconds]
234-
report_time "EXPORT IP" $time_start $time_end
228+
puts "***** EXPORT IP *****"
229+
set time_start [clock clicks -milliseconds]
230+
export_design -format ip_catalog
231+
set time_end [clock clicks -milliseconds]
232+
report_time "EXPORT IP" $time_start $time_end
235233
}
236234

237235
if {$opt(vsynth)} {
238-
puts "***** VIVADO SYNTHESIS *****"
239-
if {[file exist ${myproject}_prj/solution1/syn/vhdl]} {
240-
set time_start [clock clicks -milliseconds]
241-
exec vivado -mode batch -source vivado_synth.tcl >@ stdout
242-
set time_end [clock clicks -milliseconds]
243-
report_time "VIVADO SYNTHESIS" $time_start $time_end
244-
} else {
245-
puts "ERROR: Cannot find generated VHDL files. Did you run C synthesis?"
246-
exit 1
247-
}
236+
puts "***** VIVADO SYNTHESIS *****"
237+
if {[file exist ${project_name}_prj/solution1/syn/vhdl]} {
238+
set time_start [clock clicks -milliseconds]
239+
exec vivado -mode batch -source vivado_synth.tcl >@ stdout
240+
set time_end [clock clicks -milliseconds]
241+
report_time "VIVADO SYNTHESIS" $time_start $time_end
242+
} else {
243+
puts "ERROR: Cannot find generated VHDL files. Did you run C synthesis?"
244+
exit 1
245+
}
248246
}
249247

250248
exit

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