minor fixes

Author: alex-yang-upenn

hls4ml/templates/vitis_accelerator/Makefile

@@ -43,9 +43,9 @@ WRAPPER_NAME := kernel_wrapper
 # Top level build directory
 BUILD_DIR := ./build_$(TARGET)
 ifdef DEBUG
-BUILD_DIR += _deb
+BUILD_DIR := $(BUILD_DIR)_deb
 else
-BUILD_DIR += _rel
+BUILD_DIR := $(BUILD_DIR)_rel
 endif
 
 # Directories for kernel synthesis
@@ -70,7 +70,7 @@ else
 # Optimization flags can be added here
 endif
 
-.PHONY: all xclbin hls clean cleanhls cleanxclbin
+.PHONY: all xclbin hls clean cleanhls cleanxclbin ultraclean
 
 all: xclbin host
 

hls4ml/writer/vitis_accelerator_writer.py

@@ -167,7 +167,7 @@ def write_host(self, model):
             if '// hls-fpga-machine-learning FPGA type' in line:
                 fpgaType = 'HbmFpga' if memoryType == 'hbm' else ('DdrFpga' if memoryType == 'ddr' else 'DdrFpga')
                 dataType = '<float, float>' if isHwQuant else '<in_buffer_t, out_buffer_t>'
-                newline = fpgaType + dataType + ' fpga(BATCHSIZE * INSTREAMSIZE, BATCHSIZE * OUTSTREAMSIZE, NUM_CU, NUM_THREAD, 10);'
+                newline = '\t' + fpgaType + dataType + ' fpga(BATCHSIZE * INSTREAMSIZE, BATCHSIZE * OUTSTREAMSIZE, NUM_CU, NUM_THREAD, 10);'
             elif '/*IN_TYPE_CAST*/' in line:
                 newline = line.replace('/*IN_TYPE_CAST*/', '' if isHwQuant else '(in_buffer_t)')
             elif '/*OUT_TYPE_CAST*/' in line:
@@ -207,8 +207,7 @@ def write_makefile(self, model):
             if 'myproject' in line:
                 newline = line.replace('myproject', project_name)
             if 'BOARD_TYPE :=' in line:
-                newline = line
-                newline += board_type
+                newline += 'BOARD_TYPE := ' + board_type + '\n'
             else:
                 newline = line
             fout.write(newline)