edited the linker cmd file to re locate ipc ram on GSRAM to comply with device support lnk cmd files

Author: fededc88

cmd/2837xD_RAM_IPCLIB_lnk_cpu1.cmd

@@ -31,16 +31,16 @@ PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unifie
 SECTIONS
 {
 
-   .cpul_cpur_data            : > RAMGS3,       PAGE = 1
+   .cpul_cpur_data            : > RAMGS4,       PAGE = 1
 
-   GROUP               : > RAMGS5,       PAGE = 1
+   GROUP               : > RAMGS6,       PAGE = 1
    {
-         .base_cpul_cpur_addr            /* allocate base_ramgs5 to RAMSG5_BASE specific address */
+         .base_cpul_cpur_addr            /* allocate base_ramgs6 to RAMSG6_BASE specific address */
          .cpul_cpur_addr               
    }
-   GROUP               : > RAMGS6,       PAGE = 1
+   GROUP               : > RAMGS7,       PAGE = 1
    {
-         .base_cpur_cpul_addr            /* allocate base_ramgs6 to RAMSG6_BASE specific address */
+         .base_cpur_cpul_addr            /* allocate base_ramgs7 to RAMSG7_BASE specific address */
          .cpur_cpul_addr              
    }
 

cmd/2837xD_RAM_IPCLIB_lnk_cpu2.cmd

@@ -31,16 +31,16 @@ PAGE 1 : /* Data memory. This is a legacy description since the C28 has a unifie
 SECTIONS
 {
 
-   .cpul_cpur_data            : > RAMGS1,       PAGE = 1
+   .cpul_cpur_data            : > RAMGS2,       PAGE = 1
 
-   GROUP               : > RAMGS5,       PAGE = 1
+   GROUP               : > RAMGS6,       PAGE = 1
    {
-         .base_cpur_cpul_addr            /* allocate base_ramgs5 to RAMSG5_BASE specific address */
+         .base_cpur_cpul_addr            /* allocate base_ramgs6 to RAMSG6_BASE specific address */
          .cpur_cpul_addr               
    }
-   GROUP               : > RAMGS6,       PAGE = 1
+   GROUP               : > RAMGS7,       PAGE = 1
    {
-         .base_cpul_cpur_addr            /* allocate base_ramgs6 to RAMSG6_BASE specific address */
+         .base_cpul_cpur_addr            /* allocate base_ramgs7 to RAMSG7_BASE specific address */
          .cpul_cpur_addr              
    }
 

include/ipc_defs.h

@@ -27,20 +27,21 @@
 #endif
 
 // gsxm blocks that master cpu1 reserverd for ipc driver app
-#define APIPC_CPU01_TO_CPU02_GSxRAM GS3_ACCESS|GS4_ACCESS|GS5_ACCESS
+#define APIPC_CPU01_TO_CPU02_GSxRAM GS4_ACCESS|GS5_ACCESS|GS6_ACCESS
 // gsxm blocks that master cpu2 reserverd for ipc driver app
-#define APIPC_CPU02_TO_CPU01_GSxRAM GS1_ACCESS|GS2_ACCESS|GS6_ACCESS
+#define APIPC_CPU02_TO_CPU01_GSxRAM GS2_ACCESS|GS3_ACCESS|GS7_ACCESS
 
-//GS3SARAM Start Address
-#define CPU01_TO_CPU02_R_W_DATA_START (uint32_t)0x0000F000  
+//GS4SARAM Start Address
+#define CPU01_TO_CPU02_R_W_DATA_START (uint32_t)0x00010000  
 
 // CPU01 to CPU02 Local Addresses MSG RAM off sets
-#define CPU01_TO_CPU02_R_W_ADDR (uint32_t)0x00011000  					              // for passing address
+#define CPU01_TO_CPU02_R_W_ADDR (uint32_t)0x00012000  					              // for passing address
 
-#define CPU02_TO_CPU01_R_W_DATA_START (uint32_t)0x0000D000 
+//GS2SARAM Start Address
+#define CPU02_TO_CPU01_R_W_DATA_START (uint32_t)0x0000E000 
 
 // CPU02 to CPU01 Local Addresses MSG RAM offsets
-#define CPU02_TO_CPU01_R_W_ADDR (uint32_t)0x00012000  
+#define CPU02_TO_CPU01_R_W_ADDR (uint32_t)0x00013000  
 
 // Local R_W_DATA length space
 #define CL_R_W_DATA_LENGTH 4096