dft: renaming main dft tcl commands

fgaray · fgaray · commit aa5188456528 · 2025-06-20T11:35:46.000-07:00
preview_dft =&gt; report_dft_plan
insert_dft =&gt; execute_dft_plan

Signed-off-by: Felipe Garay &lt;fgaray@google.com&gt;
diff --git a/src/dft/README.md b/src/dft/README.md
@@ -47,8 +47,8 @@ in `no_mix` clock mode it specifies a maximum number of chains per clock-edge pa
 
 ### Report DFT Config
 
-Prints the current DFT configuration to be used by `preview_dft` and
-`insert_dft`.
+Prints the current DFT configuration to be used by `report_dft_plan` and
+`execute_dft_plan`.
 
 ```tcl
 report_dft_config
@@ -63,15 +63,15 @@ placement, as it changes the area of cells.
 scan_replace
 ```
 
-### Preview DFT
+### Report DFT Plan
 
-Prints a preview of the scan chains that will be stitched by `insert_dft`. Use
+Prints a preview of the scan chains that will be stitched by `execute_dft_plan`. Use
 this command to iterate and try different DFT configurations. This command does
 not perform any modification to the design, and should be run after `scan_replace`
 and global placement.
 
 ```tcl
-preview_dft
+report_dft_plan
     [-verbose]
 ```
 
@@ -81,13 +81,13 @@ preview_dft
 | ---- | ---- |
 | `-verbose` | Shows more information about each one of the scan chains that will be created. |
 
-### Insert DFT
+### Execute DFT Plan
 
 Architect scan chains and connect them up in a way that minimises wirelength. As
 a result, this should be run after placement, and after `scan_replace`.
 
 ```tcl
-insert_dft
+execute_dft_plan
 ```
 
 ## Example scripts
@@ -100,8 +100,8 @@ set_dft_config -max_length 10 -clock_mixing clock_mix
 report_dft_config
 scan_replace
 # Run global placement...
-preview_dft -verbose
-insert_dft
+report_dft_plan -verbose
+execute_dft_plan
 ```
 
 ## Regression tests
diff --git a/src/dft/include/dft/Dft.hh b/src/dft/include/dft/Dft.hh
@@ -57,7 +57,7 @@ class Dft
   //
   // If verbose is true, then we show all the cells that are inside the scan
   // chains
-  void previewDft(bool verbose);
+  void reportDftPlan(bool verbose);
 
   // Inserts the scan chains into the design. For now this just replace the
   // cells in the design with scan equivalent. This functions mutates the
@@ -68,7 +68,14 @@ class Dft
   //
   void scanReplace();
 
-  void insertDft();
+  // Runs the complete flow for scan insertion based on the user's settings
+  //
+  // Here we do:
+  //  - Scan Replace
+  //  - Scan Architect
+  //  - Scan Insertion
+  //  - Store the inserted DFT (scan chains) into odb for later optimization
+  void executeDftPlan();
 
   // Returns a mutable version of DftConfig
   DftConfig* getMutableDftConfig();
@@ -87,7 +94,7 @@ class Dft
   void reset();
 
   // Common function to perform scan replace and scan architect. Shared between
-  // preview_dft and insert_dft
+  // report_dft_plan and execute_dft_plan
   std::vector<std::unique_ptr<ScanChain>> scanArchitect();
 
   // Global state
diff --git a/src/dft/src/Dft.cpp b/src/dft/src/Dft.cpp
@@ -56,7 +56,7 @@ void Dft::pre_dft()
   need_to_run_pre_dft_ = false;
 }
 
-void Dft::previewDft(bool verbose)
+void Dft::reportDftPlan(bool verbose)
 {
   if (need_to_run_pre_dft_) {
     pre_dft();
@@ -65,7 +65,7 @@ void Dft::previewDft(bool verbose)
   std::vector<std::unique_ptr<ScanChain>> scan_chains = scanArchitect();
 
   logger_->report("***************************");
-  logger_->report("Preview DFT Report");
+  logger_->report("Report DFT Plan");
   logger_->report("Number of chains: {:d}", scan_chains.size());
   logger_->report("Clock domain: {:s}",
                   ScanArchitectConfig::ClockMixingName(
@@ -85,7 +85,7 @@ void Dft::scanReplace()
   scan_replace_->scanReplace();
 }
 
-void Dft::insertDft()
+void Dft::executeDftPlan()
 {
   if (need_to_run_pre_dft_) {
     pre_dft();
diff --git a/src/dft/src/dft.i b/src/dft/src/dft.i
@@ -70,19 +70,19 @@ utl::Logger* getLogger()
 %inline
 %{
 
-void preview_dft(bool verbose)
+void report_dft_plan(bool verbose)
 {
-  getDft()->previewDft(verbose);
+  getDft()->reportDftPlan(verbose);
 }
 
 void scan_replace()
 {
   getDft()->scanReplace();
 }
 
-void insert_dft()
+void execute_dft_plan()
 {
-  getDft()->insertDft();
+  getDft()->executeDftPlan();
 }
 
 void set_dft_config_max_length(int max_length)
diff --git a/src/dft/src/dft.tcl b/src/dft/src/dft.tcl
@@ -1,22 +1,22 @@
 # SPDX-License-Identifier: BSD-3-Clause
 # Copyright (c) 2023-2025, The OpenROAD Authors
 
-sta::define_cmd_args "preview_dft" {[-verbose]}
+sta::define_cmd_args "report_dft_plan" {[-verbose]}
 
-proc preview_dft { args } {
-  sta::parse_key_args "preview_dft" args \
+proc report_dft_plan { args } {
+  sta::parse_key_args "report_dft_plan" args \
     keys {} \
     flags {-verbose}
 
-  sta::check_argc_eq0 "preview_dft" $args
+  sta::check_argc_eq0 "report_dft_plan" $args
 
   if { [ord::get_db_block] == "NULL" } {
     utl::error DFT 1 "No design block found."
   }
 
   set verbose [info exists flags(-verbose)]
 
-  dft::preview_dft $verbose
+  dft::report_dft_plan $verbose
 }
 
 sta::define_cmd_args "scan_replace" { }
@@ -30,16 +30,16 @@ proc scan_replace { args } {
   dft::scan_replace
 }
 
-sta::define_cmd_args "insert_dft" {}
-proc insert_dft { args } {
-  sta::parse_key_args "insert_dft" args \
+sta::define_cmd_args "execute_dft_plan" {}
+proc execute_dft_plan { args } {
+  sta::parse_key_args "execute_dft_plan" args \
     keys {} \
     flags {}
 
   if { [ord::get_db_block] == "NULL" } {
     utl::error DFT 9 "No design block found."
   }
-  dft::insert_dft
+  dft::execute_dft_plan
 }
 
 sta::define_cmd_args "set_dft_config" { [-max_length max_length]
diff --git a/src/dft/test/max_chain_count_sky130.ok b/src/dft/test/max_chain_count_sky130.ok
@@ -1,7 +1,7 @@
 [INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias
 [INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells
 ***************************
-Preview DFT Report
+Report DFT Plan
 Number of chains: 1
 Clock domain: No Mix
 ***************************
diff --git a/src/dft/test/max_chain_count_sky130.tcl b/src/dft/test/max_chain_count_sky130.tcl
@@ -13,8 +13,8 @@ set_dft_config -max_length 4 -max_chains 1
 
 scan_replace
 
-preview_dft -verbose
-insert_dft
+report_dft_plan -verbose
+execute_dft_plan
 
 set verilog_file [make_result_file max_chain_count_sky130.v]
 write_verilog $verilog_file
diff --git a/src/dft/test/one_cell_sky130.ok b/src/dft/test/one_cell_sky130.ok
@@ -28,7 +28,7 @@ Instance ff1
   Q output output1
   Q_N output (unconnected)
 ***************************
-Preview DFT Report
+Report DFT Plan
 Number of chains: 1
 Clock domain: No Mix
 ***************************
diff --git a/src/dft/test/one_cell_sky130.tcl b/src/dft/test/one_cell_sky130.tcl
@@ -13,9 +13,9 @@ set_dft_config -max_length 10
 report_instance ff1
 scan_replace
 report_instance ff1
-preview_dft -verbose
+report_dft_plan -verbose
 report_instance ff1
-insert_dft
+execute_dft_plan
 report_instance ff1
 
 set verilog_file [make_result_file one_cell_sky130.v]
diff --git a/src/dft/test/place_sort_sky130.ok b/src/dft/test/place_sort_sky130.ok
@@ -1,7 +1,7 @@
 [INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias
 [INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells
 ***************************
-Preview DFT Report
+Report DFT Plan
 Number of chains: 1
 Clock domain: No Mix
 ***************************
diff --git a/src/dft/test/place_sort_sky130.tcl b/src/dft/test/place_sort_sky130.tcl
@@ -31,8 +31,8 @@ place_inst ff8_clk1_rising  4000 3000
 place_inst ff9_clk1_rising  8000 8000
 place_inst ff10_clk1_rising 3000 3000
 
-preview_dft -verbose
-insert_dft
+report_dft_plan -verbose
+execute_dft_plan
 
 set verilog_file [make_result_file place_sort_sky130.v]
 write_verilog $verilog_file
diff --git a/src/dft/test/scan_architect_clock_mix_sky130.ok b/src/dft/test/scan_architect_clock_mix_sky130.ok
@@ -1,7 +1,7 @@
 [INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias
 [INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells
 ***************************
-Preview DFT Report
+Report DFT Plan
 Number of chains: 7
 Clock domain: Clock Mix
 ***************************
diff --git a/src/dft/test/scan_architect_clock_mix_sky130.tcl b/src/dft/test/scan_architect_clock_mix_sky130.tcl
@@ -17,7 +17,7 @@ scan_replace
 set verilog_file_before_preview [make_result_file scan_architect_clock_mix_sky130_before_preview.v]
 write_verilog -sort $verilog_file_before_preview
 
-preview_dft -verbose
+report_dft_plan -verbose
 
 # Preview should not modify the net
 set verilog_file_after_preview [make_result_file scan_architect_clock_mix_sky130_after_preview.v]
@@ -26,7 +26,7 @@ write_verilog -sort $verilog_file_after_preview
 # Before and after preview, the netlist should be the same
 diff_files $verilog_file_after_preview $verilog_file_before_preview
 
-insert_dft
+execute_dft_plan
 
 set verilog_file [make_result_file scan_architect_clock_mix_sky130.v]
 write_verilog $verilog_file
diff --git a/src/dft/test/scan_architect_no_mix_sky130.ok b/src/dft/test/scan_architect_no_mix_sky130.ok
@@ -1,7 +1,7 @@
 [INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias
 [INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells
 ***************************
-Preview DFT Report
+Report DFT Plan
 Number of chains: 4
 Clock domain: No Mix
 ***************************
diff --git a/src/dft/test/scan_architect_no_mix_sky130.tcl b/src/dft/test/scan_architect_no_mix_sky130.tcl
@@ -17,7 +17,7 @@ scan_replace
 set verilog_file_before_preview [make_result_file scan_architect_no_mix_sky130_before_preview.v]
 write_verilog -sort $verilog_file_before_preview
 
-preview_dft -verbose
+report_dft_plan -verbose
 
 # Preview should not modify the net
 set verilog_file_after_preview [make_result_file scan_architect_no_mix_sky130_after_preview.v]
@@ -26,7 +26,7 @@ write_verilog -sort $verilog_file_after_preview
 # Before and after preview, the netlist should be the same
 diff_files $verilog_file_after_preview $verilog_file_before_preview
 
-insert_dft
+execute_dft_plan
 
 set verilog_file [make_result_file scan_architect_no_mix_sky130.v]
 write_verilog $verilog_file
diff --git a/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.ok b/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.ok
@@ -1,7 +1,7 @@
 [INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias
 [INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells
 ***************************
-Preview DFT Report
+Report DFT Plan
 Number of chains: 2
 Clock domain: No Mix
 ***************************
diff --git a/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.tcl b/src/dft/test/scan_architect_register_bank_no_clock_mix_sky130.tcl
@@ -13,8 +13,8 @@ create_clock -name clk2 -period 2.0000 -waveform {0.0000 1.0000} [get_ports {clk
 set_dft_config -max_length 20000 -clock_mixing no_mix
 
 scan_replace
-preview_dft -verbose
-insert_dft
+report_dft_plan -verbose
+execute_dft_plan
 
 set verilog_file [make_result_file scan_architect_register_bank_no_clock_mix_sky130.v]
 write_verilog $verilog_file
diff --git a/src/dft/test/sub_modules_sky130.ok b/src/dft/test/sub_modules_sky130.ok
@@ -1,7 +1,7 @@
 [INFO ODB-0227] LEF file: sky130hd/sky130hd.tlef, created 13 layers, 25 vias
 [INFO ODB-0227] LEF file: sky130hd/sky130_fd_sc_hd_merged.lef, created 437 library cells
 ***************************
-Preview DFT Report
+Report DFT Plan
 Number of chains: 1
 Clock domain: No Mix
 ***************************
diff --git a/src/dft/test/sub_modules_sky130.tcl b/src/dft/test/sub_modules_sky130.tcl
@@ -10,8 +10,8 @@ link_design sub_modules
 create_clock -name main_clock -period 2.0000 -waveform {0.0000 1.0000} [get_ports {clock}]
 
 scan_replace
-preview_dft -verbose
-insert_dft
+report_dft_plan -verbose
+execute_dft_plan
 
 set verilog_file [make_result_file sub_modules_sky130.v]
 write_verilog $verilog_file

Original file line number	Diff line number	Diff line change
`@@ -56,7 +56,7 @@ void Dft::pre_dft()`
`56`	`56`	`need_to_run_pre_dft_ = false;`
`57`	`57`	`}`
`58`	`58`
`59`		`-void Dft::previewDft(bool verbose)`
	`59`	`+void Dft::reportDftPlan(bool verbose)`
`60`	`60`	`{`
`61`	`61`	`if (need_to_run_pre_dft_) {`
`62`	`62`	`pre_dft();`
`@@ -65,7 +65,7 @@ void Dft::previewDft(bool verbose)`
`65`	`65`	`std::vector<std::unique_ptr<ScanChain>> scan_chains = scanArchitect();`
`66`	`66`
`67`	`67`	`logger_->report("***************************");`
`68`		`- logger_->report("Preview DFT Report");`
	`68`	`+ logger_->report("Report DFT Plan");`
`69`	`69`	`logger_->report("Number of chains: {:d}", scan_chains.size());`
`70`	`70`	`logger_->report("Clock domain: {:s}",`
`71`	`71`	`ScanArchitectConfig::ClockMixingName(`
`@@ -85,7 +85,7 @@ void Dft::scanReplace()`
`85`	`85`	`scan_replace_->scanReplace();`
`86`	`86`	`}`
`87`	`87`
`88`		`-void Dft::insertDft()`
	`88`	`+void Dft::executeDftPlan()`
`89`	`89`	`{`
`90`	`90`	`if (need_to_run_pre_dft_) {`
`91`	`91`	`pre_dft();`
Original file line number	Diff line number	Diff line change
`@@ -70,19 +70,19 @@ utl::Logger* getLogger()`
`70`	`70`	`%inline`
`71`	`71`	`%{`
`72`	`72`
`73`		`-void preview_dft(bool verbose)`
	`73`	`+void report_dft_plan(bool verbose)`
`74`	`74`	`{`
`75`		`- getDft()->previewDft(verbose);`
	`75`	`+ getDft()->reportDftPlan(verbose);`
`76`	`76`	`}`
`77`	`77`
`78`	`78`	`void scan_replace()`
`79`	`79`	`{`
`80`	`80`	`getDft()->scanReplace();`
`81`	`81`	`}`
`82`	`82`
`83`		`-void insert_dft()`
	`83`	`+void execute_dft_plan()`
`84`	`84`	`{`
`85`		`- getDft()->insertDft();`
	`85`	`+ getDft()->executeDftPlan();`
`86`	`86`	`}`
`87`	`87`
`88`	`88`	`void set_dft_config_max_length(int max_length)`