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[Target] Migrate away from PointerUnion::{is,get,dyn_cast} (NFC) (llvm#115623)
Note that PointerUnion::{is,get,dyn_cast} have been soft deprecated in PointerUnion.h: // FIXME: Replace the uses of is(), get() and dyn_cast() with // isa<T>, cast<T> and the llvm::dyn_cast<T>
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7 files changed

+21
-21
lines changed

7 files changed

+21
-21
lines changed

‎llvm/lib/Target/AArch64/GISel/AArch64InstructionSelector.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -995,9 +995,9 @@ static bool selectDebugInstr(MachineInstr &I, MachineRegisterInfo &MRI,
995995
LLT Ty = MRI.getType(Reg);
996996
const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
997997
const TargetRegisterClass *RC =
998-
RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
998+
dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
999999
if (!RC) {
1000-
const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
1000+
const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
10011001
RC = getRegClassForTypeOnBank(Ty, RB);
10021002
if (!RC) {
10031003
LLVM_DEBUG(
@@ -2590,14 +2590,14 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
25902590
const RegClassOrRegBank &RegClassOrBank =
25912591
MRI.getRegClassOrRegBank(DefReg);
25922592

2593-
const TargetRegisterClass *DefRC
2594-
= RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
2593+
const TargetRegisterClass *DefRC =
2594+
dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
25952595
if (!DefRC) {
25962596
if (!DefTy.isValid()) {
25972597
LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
25982598
return false;
25992599
}
2600-
const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
2600+
const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
26012601
DefRC = getRegClassForTypeOnBank(DefTy, RB);
26022602
if (!DefRC) {
26032603
LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
@@ -4677,7 +4677,7 @@ AArch64InstructionSelector::emitCSINC(Register Dst, Register Src1,
46774677
// If we used a register class, then this won't necessarily have an LLT.
46784678
// Compute the size based off whether or not we have a class or bank.
46794679
unsigned Size;
4680-
if (const auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
4680+
if (const auto *RC = dyn_cast<const TargetRegisterClass *>(RegClassOrBank))
46814681
Size = TRI.getRegSizeInBits(*RC);
46824682
else
46834683
Size = MRI.getType(Dst).getSizeInBits();

‎llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -81,7 +81,7 @@ bool AMDGPUInstructionSelector::isVCC(Register Reg,
8181

8282
auto &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
8383
const TargetRegisterClass *RC =
84-
RegClassOrBank.dyn_cast<const TargetRegisterClass*>();
84+
dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
8585
if (RC) {
8686
const LLT Ty = MRI.getType(Reg);
8787
if (!Ty.isValid() || Ty.getSizeInBits() != 1)
@@ -91,7 +91,7 @@ bool AMDGPUInstructionSelector::isVCC(Register Reg,
9191
RC->hasSuperClassEq(TRI.getBoolRC());
9292
}
9393

94-
const RegisterBank *RB = RegClassOrBank.get<const RegisterBank *>();
94+
const RegisterBank *RB = cast<const RegisterBank *>(RegClassOrBank);
9595
return RB->getID() == AMDGPU::VCCRegBankID;
9696
}
9797

@@ -233,15 +233,15 @@ bool AMDGPUInstructionSelector::selectPHI(MachineInstr &I) const {
233233
const RegClassOrRegBank &RegClassOrBank =
234234
MRI->getRegClassOrRegBank(DefReg);
235235

236-
const TargetRegisterClass *DefRC
237-
= RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
236+
const TargetRegisterClass *DefRC =
237+
dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
238238
if (!DefRC) {
239239
if (!DefTy.isValid()) {
240240
LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
241241
return false;
242242
}
243243

244-
const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
244+
const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
245245
DefRC = TRI.getRegClassForTypeOnBank(DefTy, RB);
246246
if (!DefRC) {
247247
LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");
@@ -2395,11 +2395,11 @@ const RegisterBank *AMDGPUInstructionSelector::getArtifactRegBank(
23952395
Register Reg, const MachineRegisterInfo &MRI,
23962396
const TargetRegisterInfo &TRI) const {
23972397
const RegClassOrRegBank &RegClassOrBank = MRI.getRegClassOrRegBank(Reg);
2398-
if (auto *RB = RegClassOrBank.dyn_cast<const RegisterBank *>())
2398+
if (auto *RB = dyn_cast<const RegisterBank *>(RegClassOrBank))
23992399
return RB;
24002400

24012401
// Ignore the type, since we don't use vcc in artifacts.
2402-
if (auto *RC = RegClassOrBank.dyn_cast<const TargetRegisterClass *>())
2402+
if (auto *RC = dyn_cast<const TargetRegisterClass *>(RegClassOrBank))
24032403
return &RBI.getRegBankFromRegClass(*RC, LLT());
24042404
return nullptr;
24052405
}

‎llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3682,10 +3682,10 @@ const TargetRegisterClass *
36823682
SIRegisterInfo::getConstrainedRegClassForOperand(const MachineOperand &MO,
36833683
const MachineRegisterInfo &MRI) const {
36843684
const RegClassOrRegBank &RCOrRB = MRI.getRegClassOrRegBank(MO.getReg());
3685-
if (const RegisterBank *RB = RCOrRB.dyn_cast<const RegisterBank*>())
3685+
if (const RegisterBank *RB = dyn_cast<const RegisterBank *>(RCOrRB))
36863686
return getRegClassForTypeOnBank(MRI.getType(MO.getReg()), *RB);
36873687

3688-
if (const auto *RC = RCOrRB.dyn_cast<const TargetRegisterClass *>())
3688+
if (const auto *RC = dyn_cast<const TargetRegisterClass *>(RCOrRB))
36893689
return getAllocatableClass(RC);
36903690

36913691
return nullptr;

‎llvm/lib/Target/BPF/BPFAbstractMemberAccess.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -303,7 +303,7 @@ static uint32_t calcArraySize(const DICompositeType *CTy, uint32_t StartDim) {
303303
if (auto *Element = dyn_cast_or_null<DINode>(Elements[I]))
304304
if (Element->getTag() == dwarf::DW_TAG_subrange_type) {
305305
const DISubrange *SR = cast<DISubrange>(Element);
306-
auto *CI = SR->getCount().dyn_cast<ConstantInt *>();
306+
auto *CI = dyn_cast<ConstantInt *>(SR->getCount());
307307
DimSize *= CI->getSExtValue();
308308
}
309309
}

‎llvm/lib/Target/BPF/BTFDebug.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -715,7 +715,7 @@ void BTFDebug::visitArrayType(const DICompositeType *CTy, uint32_t &TypeId) {
715715
if (auto *Element = dyn_cast_or_null<DINode>(Elements[I]))
716716
if (Element->getTag() == dwarf::DW_TAG_subrange_type) {
717717
const DISubrange *SR = cast<DISubrange>(Element);
718-
auto *CI = SR->getCount().dyn_cast<ConstantInt *>();
718+
auto *CI = dyn_cast<ConstantInt *>(SR->getCount());
719719
int64_t Count = CI->getSExtValue();
720720

721721
// For struct s { int b; char c[]; }, the c[] will be represented

‎llvm/lib/Target/RISCV/GISel/RISCVInstructionSelector.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -598,14 +598,14 @@ bool RISCVInstructionSelector::select(MachineInstr &MI) {
598598
MRI->getRegClassOrRegBank(DefReg);
599599

600600
const TargetRegisterClass *DefRC =
601-
RegClassOrBank.dyn_cast<const TargetRegisterClass *>();
601+
dyn_cast<const TargetRegisterClass *>(RegClassOrBank);
602602
if (!DefRC) {
603603
if (!DefTy.isValid()) {
604604
LLVM_DEBUG(dbgs() << "PHI operand has no type, not a gvreg?\n");
605605
return false;
606606
}
607607

608-
const RegisterBank &RB = *RegClassOrBank.get<const RegisterBank *>();
608+
const RegisterBank &RB = *cast<const RegisterBank *>(RegClassOrBank);
609609
DefRC = getRegClassForTypeOnBank(DefTy, RB);
610610
if (!DefRC) {
611611
LLVM_DEBUG(dbgs() << "PHI operand has unexpected size/bank\n");

‎llvm/lib/Target/WebAssembly/WebAssemblyMachineFunctionInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -141,8 +141,8 @@ yaml::WebAssemblyFunctionInfo::WebAssemblyFunctionInfo(
141141
for (const auto &MBB : MF)
142142
MBBs.insert(&MBB);
143143
for (auto KV : EHInfo->SrcToUnwindDest) {
144-
auto *SrcBB = KV.first.get<MachineBasicBlock *>();
145-
auto *DestBB = KV.second.get<MachineBasicBlock *>();
144+
auto *SrcBB = cast<MachineBasicBlock *>(KV.first);
145+
auto *DestBB = cast<MachineBasicBlock *>(KV.second);
146146
if (MBBs.count(SrcBB) && MBBs.count(DestBB))
147147
SrcToUnwindDest[SrcBB->getNumber()] = DestBB->getNumber();
148148
}

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