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!Fixup update after merge
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9 files changed

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-49
lines changed

9 files changed

+38
-49
lines changed

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -622,6 +622,7 @@ class VPBlockBase {
622622
void clearSuccessors() { Successors.clear(); }
623623

624624
/// Swap successors of the block. The block must have exactly 2 successors.
625+
// TODO: This should be part of introducing conditional branch recipes rather than being independent.
625626
void swapSuccessors() {
626627
assert(Successors.size() == 2 && "must have 2 successors to swap");
627628
std::swap(Successors[0], Successors[1]);
@@ -3766,6 +3767,7 @@ class VPlan {
37663767
/// VPBasicBlock corresponding to the original preheader. Used to place
37673768
/// VPExpandSCEV recipes for expressions used during skeleton creation and the
37683769
/// rest of VPlan execution.
3770+
/// When this VPlan is used for the epilogue vector loop, the entry will be replaced by a new entry block created during skeleton creation.
37693771
VPBasicBlock *Entry;
37703772

37713773
/// VPIRBasicBlock wrapping the header of the original scalar loop.
@@ -3846,14 +3848,8 @@ class VPlan {
38463848
/// Create initial VPlan, having an "entry" VPBasicBlock (wrapping
38473849
/// original scalar pre-header) which contains SCEV expansions that need
38483850
/// to happen before the CFG is modified (when executing a VPlan for the
3849-
/// epilogue vector loop, the original entry needs to be replaced by the new
3850-
/// entry for the epilogue vector loop); a VPBasicBlock for the vector
3851-
/// pre-header, followed by a region for the vector loop, followed by the
3852-
/// middle VPBasicBlock. If a check is needed to guard executing the scalar
3853-
/// epilogue loop, it will be added to the middle block, together with
3854-
/// VPBasicBlocks for the scalar preheader and exit blocks.
3855-
/// \p InductionTy is the type of the canonical induction and used for related
3856-
/// values, like the trip count expression.
3851+
/// epilogue vector loop, the original entry needs to be replaced by a new
3852+
/// one); a VPBasicBlock for the vector pre-header, followed by a region for the vector loop, followed by the middle VPBasicBlock. If a check is needed to guard executing the scalar epilogue loop, it will be added to the middle block, together with VPBasicBlocks for the scalar preheader and exit blocks. \p InductionTy is the type of the canonical induction and used for related values, like the trip count expression.
38573853
static VPlanPtr createInitialVPlan(Type *InductionTy,
38583854
PredicatedScalarEvolution &PSE,
38593855
bool RequiresScalarEpilogueCheck,

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -40,24 +40,15 @@
4040
; IF-EVL-NEXT: WIDEN ir<[[LD2:%.+]]> = vp.load vp<[[PTR2]]>, vp<[[EVL]]>
4141
; IF-EVL-NEXT: WIDEN ir<[[CMP:%.+]]> = icmp sgt ir<[[LD1]]>, ir<[[LD2]]>
4242
; IF-EVL-NEXT: WIDEN ir<[[SUB:%.+]]> = vp.sub ir<0>, ir<[[LD2]]>, vp<[[EVL]]>
43-
<<<<<<< HEAD
44-
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[SELECT:%.+]]> = call llvm.vp.select(ir<[[CMP]]>, ir<%10>, ir<%11>, vp<[[EVL]]>)
45-
=======
4643
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[SELECT:%.+]]> = call llvm.vp.select(ir<[[CMP]]>, ir<[[LD2]]>, ir<[[SUB]]>, vp<[[EVL]]>)
47-
>>>>>>> origin/main
4844
; IF-EVL-NEXT: WIDEN ir<[[ADD:%.+]]> = vp.add vp<[[SELECT]]>, ir<[[LD1]]>, vp<[[EVL]]>
4945
; IF-EVL-NEXT: CLONE ir<[[GEP3:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
5046
; IF-EVL-NEXT: vp<[[PTR3:%.+]]> = vector-pointer ir<[[GEP3]]>
5147
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR3]]>, ir<[[ADD]]>, vp<[[EVL]]>
5248
; IF-EVL-NEXT: SCALAR-CAST vp<[[CAST:%[0-9]+]]> = zext vp<[[EVL]]> to i64
5349
; IF-EVL-NEXT: EMIT vp<[[IV_NEX]]> = add vp<[[CAST]]>, vp<[[EVL_PHI]]>
54-
<<<<<<< HEAD
55-
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT_EXIT]]> = add vp<[[IV]]>, ir<%8>
56-
; IF-EVL-NEXT: EMIT branch-on-count vp<[[IV_NEXT_EXIT]]>, ir<%n.vec>
57-
=======
5850
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT_EXIT]]> = add vp<[[IV]]>, ir<[[VFUF]]>
5951
; IF-EVL-NEXT: EMIT branch-on-count vp<[[IV_NEXT_EXIT]]>, ir<[[VTC]]>
60-
>>>>>>> origin/main
6152
; IF-EVL-NEXT: No successors
6253
; IF-EVL-NEXT: }
6354

‎llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -99,6 +99,9 @@ define void @test_tc_less_than_16(ptr %A, i64 %N) {
9999
; CHECK-NEXT: EMIT branch-on-cond vp<[[C]]>
100100
; CHECK-NEXT: Successor(s): ir-bb<exit>, ir-bb<scalar.ph>
101101
; CHECK-EMPTY:
102+
; CHECK-NEXT: ir-bb<exit>:
103+
; CHECK-NEXT: No successors
104+
; CHECK-EMPTY:
102105
; CHECK-NEXT: ir-bb<scalar.ph>:
103106
; CHECK-NEXT: EMIT vp<[[RESUME1:%.+]]> = resume-phi ir<%ind.end>, ir<%and>
104107
; CHECK-NEXT: EMIT vp<[[RESUME2:%.+]]>.1 = resume-phi ir<%ind.end1>, ir<%A>
@@ -109,9 +112,6 @@ define void @test_tc_less_than_16(ptr %A, i64 %N) {
109112
; CHECK-NEXT: IR %p.src = phi ptr [ %A, %scalar.ph ], [ %p.src.next, %loop ] (extra operand: vp<[[RESUME2]]>.1 from ir-bb<scalar.ph>)
110113
; CHECK: IR %cmp = icmp eq i64 %iv.next, 0
111114
; CHECK-NEXT: No successors
112-
; CHECK-EMPTY:
113-
; CHECK-NEXT: ir-bb<exit>:
114-
; CHECK-NEXT: No successors
115115
; CHECK-NEXT: }
116116
;
117117
entry:

‎llvm/test/Transforms/PhaseOrdering/AArch64/hoist-runtime-checks.ll

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -18,12 +18,8 @@ define i32 @read_only_loop_with_runtime_check(ptr noundef %array, i32 noundef %c
1818
; CHECK: for.body.preheader10:
1919
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 8
2020
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER13:%.*]], label [[VECTOR_PH:%.*]]
21-
; CHECK: for.body.preheader13:
22-
; CHECK-NEXT: [[INDVARS_IV_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER10]] ], [ [[N_VEC:%.*]], [[MIDDLE_BLOCK:%.*]] ]
23-
; CHECK-NEXT: [[SUM_07_PH:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER10]] ], [ [[TMP7:%.*]], [[MIDDLE_BLOCK]] ]
24-
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
2521
; CHECK: vector.ph:
26-
; CHECK-NEXT: [[N_VEC]] = and i64 [[TMP0]], 4294967288
22+
; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[TMP0]], 4294967288
2723
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
2824
; CHECK: vector.body:
2925
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
@@ -37,12 +33,16 @@ define i32 @read_only_loop_with_runtime_check(ptr noundef %array, i32 noundef %c
3733
; CHECK-NEXT: [[TMP5]] = add <4 x i32> [[WIDE_LOAD12]], [[VEC_PHI11]]
3834
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
3935
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
40-
; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
36+
; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
4137
; CHECK: middle.block:
4238
; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP5]], [[TMP4]]
43-
; CHECK-NEXT: [[TMP7]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]])
39+
; CHECK-NEXT: [[TMP7:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]])
4440
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N_VEC]], [[TMP0]]
4541
; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER13]]
42+
; CHECK: for.body.preheader13:
43+
; CHECK-NEXT: [[INDVARS_IV_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER10]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ]
44+
; CHECK-NEXT: [[SUM_07_PH:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER10]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ]
45+
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
4646
; CHECK: for.cond.cleanup:
4747
; CHECK-NEXT: [[SUM_0_LCSSA:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[TMP7]], [[MIDDLE_BLOCK]] ], [ [[ADD:%.*]], [[FOR_BODY]] ]
4848
; CHECK-NEXT: ret i32 [[SUM_0_LCSSA]]
@@ -133,12 +133,8 @@ define dso_local noundef i32 @sum_prefix_with_sum(ptr %s.coerce0, i64 %s.coerce1
133133
; CHECK: for.body.preheader8:
134134
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 8
135135
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY_PREHEADER11:%.*]], label [[VECTOR_PH:%.*]]
136-
; CHECK: for.body.preheader11:
137-
; CHECK-NEXT: [[I_07_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER8]] ], [ [[N_VEC:%.*]], [[SPAN_CHECKED_ACCESS_EXIT:%.*]] ]
138-
; CHECK-NEXT: [[RET_0_LCSSA:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER8]] ], [ [[ADD:%.*]], [[SPAN_CHECKED_ACCESS_EXIT]] ]
139-
; CHECK-NEXT: br label [[FOR_BODY1:%.*]]
140136
; CHECK: vector.ph:
141-
; CHECK-NEXT: [[N_VEC]] = and i64 [[N]], -8
137+
; CHECK-NEXT: [[N_VEC:%.*]] = and i64 [[N]], -8
142138
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
143139
; CHECK: vector.body:
144140
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[FOR_BODY]] ]
@@ -152,12 +148,16 @@ define dso_local noundef i32 @sum_prefix_with_sum(ptr %s.coerce0, i64 %s.coerce1
152148
; CHECK-NEXT: [[TMP4]] = add <4 x i32> [[WIDE_LOAD10]], [[VEC_PHI9]]
153149
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
154150
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
155-
; CHECK-NEXT: br i1 [[TMP5]], label [[SPAN_CHECKED_ACCESS_EXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
151+
; CHECK-NEXT: br i1 [[TMP5]], label [[SPAN_CHECKED_ACCESS_EXIT:%.*]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
156152
; CHECK: middle.block:
157153
; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP4]], [[TMP3]]
158-
; CHECK-NEXT: [[ADD]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]])
154+
; CHECK-NEXT: [[ADD:%.*]] = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]])
159155
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
160156
; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP]], label [[FOR_BODY_PREHEADER11]]
157+
; CHECK: for.body.preheader11:
158+
; CHECK-NEXT: [[I_07_PH:%.*]] = phi i64 [ 0, [[FOR_BODY_PREHEADER8]] ], [ [[N_VEC]], [[SPAN_CHECKED_ACCESS_EXIT]] ]
159+
; CHECK-NEXT: [[RET_0_LCSSA:%.*]] = phi i32 [ 0, [[FOR_BODY_PREHEADER8]] ], [ [[ADD]], [[SPAN_CHECKED_ACCESS_EXIT]] ]
160+
; CHECK-NEXT: br label [[FOR_BODY1:%.*]]
161161
; CHECK: for.cond.cleanup:
162162
; CHECK-NEXT: [[RET_0_LCSSA1:%.*]] = phi i32 [ 0, [[ENTRY1:%.*]] ], [ [[ADD]], [[SPAN_CHECKED_ACCESS_EXIT]] ], [ [[ADD1:%.*]], [[FOR_BODY1]] ]
163163
; CHECK-NEXT: ret i32 [[RET_0_LCSSA1]]

‎llvm/test/Transforms/PhaseOrdering/X86/hoist-load-of-baseptr.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -53,9 +53,6 @@ define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(ptr noundef nonnull align 8
5353
; O2-NEXT: br i1 [[CMP24_NOT]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER:%.*]]
5454
; O2: for.body4.preheader:
5555
; O2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[FOR_BODY4_PREHEADER9:%.*]], label [[VECTOR_BODY:%.*]]
56-
; O2: for.body4.preheader9:
57-
; O2-NEXT: [[J_05_PH:%.*]] = phi i64 [ 0, [[FOR_BODY4_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK:%.*]] ]
58-
; O2-NEXT: br label [[FOR_BODY4:%.*]]
5956
; O2: vector.body:
6057
; O2-NEXT: [[INDEX:%.*]] = phi i64 [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ], [ 0, [[FOR_BODY4_PREHEADER]] ]
6158
; O2-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 [[INDEX]]
@@ -68,9 +65,12 @@ define dso_local void @_Z7computeRSt6vectorIiSaIiEEy(ptr noundef nonnull align 8
6865
; O2-NEXT: store <4 x i32> [[TMP4]], ptr [[TMP2]], align 4, !tbaa [[TBAA0]]
6966
; O2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8
7067
; O2-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
71-
; O2-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
68+
; O2-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
7269
; O2: middle.block:
7370
; O2-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP3]], label [[FOR_BODY4_PREHEADER9]]
71+
; O2: for.body4.preheader9:
72+
; O2-NEXT: [[J_05_PH:%.*]] = phi i64 [ 0, [[FOR_BODY4_PREHEADER]] ], [ [[N_VEC]], [[MIDDLE_BLOCK]] ]
73+
; O2-NEXT: br label [[FOR_BODY4:%.*]]
7474
; O2: for.cond.cleanup:
7575
; O2-NEXT: ret void
7676
; O2: for.cond.cleanup3:

‎llvm/test/Transforms/PhaseOrdering/X86/preserve-access-group.ll

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -17,11 +17,8 @@ define void @test(i32 noundef %nface, i32 noundef %ncell, ptr noalias noundef %f
1717
; CHECK-NEXT: [[INVARIANT_GEP:%.*]] = getelementptr inbounds nuw i32, ptr [[FACE_CELL]], i64 [[TMP0]]
1818
; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[NFACE]], 4
1919
; CHECK-NEXT: br i1 [[TMP1]], label %[[FOR_BODY_PREHEADER14:.*]], label %[[VECTOR_PH:.*]]
20-
; CHECK: [[FOR_BODY_PREHEADER14]]:
21-
; CHECK-NEXT: [[INDVARS_IV_PH:%.*]] = phi i64 [ 0, %[[FOR_BODY_PREHEADER]] ], [ [[UNROLL_ITER:%.*]], %[[MIDDLE_BLOCK:.*]] ]
22-
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
2320
; CHECK: [[VECTOR_PH]]:
24-
; CHECK-NEXT: [[UNROLL_ITER]] = and i64 [[TMP0]], 2147483644
21+
; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[TMP0]], 2147483644
2522
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
2623
; CHECK: [[VECTOR_BODY]]:
2724
; CHECK-NEXT: [[INDVARS_IV_EPIL:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
@@ -40,10 +37,13 @@ define void @test(i32 noundef %nface, i32 noundef %ncell, ptr noalias noundef %f
4037
; CHECK-NEXT: tail call void @llvm.masked.scatter.v4f64.v4p0(<4 x double> [[TMP8]], <4 x ptr> [[TMP4]], i32 8, <4 x i1> splat (i1 true)), !tbaa [[TBAA5]], !llvm.access.group [[ACC_GRP4]]
4138
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDVARS_IV_EPIL]], 4
4239
; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[UNROLL_ITER]]
43-
; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
40+
; CHECK-NEXT: br i1 [[TMP9]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
4441
; CHECK: [[MIDDLE_BLOCK]]:
4542
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UNROLL_ITER]], [[TMP0]]
4643
; CHECK-NEXT: br i1 [[CMP_N]], label %[[FOR_COND_CLEANUP]], label %[[FOR_BODY_PREHEADER14]]
44+
; CHECK: [[FOR_BODY_PREHEADER14]]:
45+
; CHECK-NEXT: [[INDVARS_IV_PH:%.*]] = phi i64 [ 0, %[[FOR_BODY_PREHEADER]] ], [ [[UNROLL_ITER]], %[[MIDDLE_BLOCK]] ]
46+
; CHECK-NEXT: br label %[[FOR_BODY:.*]]
4747
; CHECK: [[FOR_COND_CLEANUP]]:
4848
; CHECK-NEXT: ret void
4949
; CHECK: [[FOR_BODY]]:

‎llvm/unittests/Transforms/Vectorize/VPlanHCFGTest.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -107,8 +107,9 @@ edge [fontname=Courier, fontsize=30]
107107
compound=true
108108
N0 [label =
109109
"ir-bb\<entry\>:\l" +
110-
"No successors\l"
110+
"Successor(s): vector.ph\l"
111111
]
112+
N0 -> N1 [ label=""]
112113
N1 [label =
113114
"vector.ph:\l" +
114115
"Successor(s): vector loop\l"

‎llvm/unittests/Transforms/Vectorize/VPlanTest.cpp

Lines changed: 5 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -747,8 +747,9 @@ compound=true
747747
N0 [label =
748748
"preheader:\l" +
749749
" EMIT vp\<%1\> = add\l" +
750-
"No successors\l"
750+
"Successor(s): bb1\l"
751751
]
752+
N0 -> N1 [ label=""]
752753
N1 [label =
753754
"bb1:\l" +
754755
" EMIT vp\<%2\> = add\l" +
@@ -840,7 +841,7 @@ vp<%1> = original trip-count
840841
841842
preheader:
842843
EMIT vp<%1> = sub
843-
No successors
844+
Successor(s): bb1
844845
845846
bb1:
846847
EMIT vp<%2> = add
@@ -864,7 +865,7 @@ vp<%1> = original trip-count
864865
865866
preheader:
866867
EMIT vp<%1> = sub
867-
No successors
868+
Successor(s): bb1
868869
869870
bb1:
870871
EMIT vp<%2> = add
@@ -888,7 +889,7 @@ vp<%1> = original trip-count
888889
889890
preheader:
890891
EMIT vp<%1> = sub
891-
No successors
892+
Successor(s): bb1
892893
893894
bb1:
894895
EMIT vp<%2> = add

‎llvm/unittests/Transforms/Vectorize/VPlanVerifierTest.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -227,14 +227,14 @@ TEST(VPVerifierTest, BlockOutsideRegionWithParent) {
227227

228228
VPRegionBlock *R1 = new VPRegionBlock(VPBB2, VPBB2, "R1");
229229
VPBlockUtils::connectBlocks(VPBB1, R1);
230-
VPBB1->setParent(R1);
231230

232231
auto TC = std::make_unique<VPValue>();
233232
LLVMContext C;
234233
auto *ScalarHeader = BasicBlock::Create(C, "");
235234
VPIRBasicBlock *ScalarHeaderVPBB = new VPIRBasicBlock(ScalarHeader);
236235
VPBlockUtils::connectBlocks(R1, ScalarHeaderVPBB);
237236
VPlan Plan(VPPH, &*TC, VPBB1, ScalarHeaderVPBB);
237+
VPBB1->setParent(R1);
238238

239239
#if GTEST_HAS_STREAM_REDIRECTION
240240
::testing::internal::CaptureStderr();

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