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!fixup address latest comments, thanks!
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-18
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10 files changed

+185
-18
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‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2432,7 +2432,6 @@ InnerLoopVectorizer::getOrCreateVectorTripCount(BasicBlock *InsertBlock) {
24322432
/// vector preheader and its predecessor, also connecting the new block to the
24332433
/// scalar preheader.
24342434
static void introduceCheckBlockInVPlan(VPlan &Plan, BasicBlock *CheckIRBB) {
2435-
24362435
VPBlockBase *ScalarPH = Plan.getScalarPreheader();
24372436
VPBlockBase *VectorPH = Plan.getVectorPreheader();
24382437
VPBlockBase *PreVectorPH = VectorPH->getSinglePredecessor();
@@ -2530,7 +2529,7 @@ void InnerLoopVectorizer::emitIterationCountCheck(BasicBlock *Bypass) {
25302529
LoopBypassBlocks.push_back(TCCheckBlock);
25312530

25322531
// TODO: Wrap LoopVectorPreHeader in VPIRBasicBlock here.
2533-
introduceCheckBlockInVPlan(Plan, nullptr);
2532+
introduceCheckBlockInVPlan(Plan, TCCheckBlock);
25342533
}
25352534

25362535
BasicBlock *InnerLoopVectorizer::emitSCEVChecks(BasicBlock *Bypass) {
@@ -7913,7 +7912,6 @@ EpilogueVectorizerMainLoop::emitIterationCountCheck(BasicBlock *Bypass,
79137912
setBranchWeights(BI, MinItersBypassWeights, /*IsExpected=*/false);
79147913
ReplaceInstWithInst(TCCheckBlock->getTerminator(), &BI);
79157914

7916-
// Connect TCCheckblock to the VPlan.
79177915
introduceCheckBlockInVPlan(Plan, TCCheckBlock);
79187916
return TCCheckBlock;
79197917
}
@@ -8068,7 +8066,7 @@ EpilogueVectorizerEpilogueLoop::emitMinimumVectorEpilogueIterCountCheck(
80688066
Plan.setEntry(NewEntry);
80698067
delete OldEntry;
80708068

8071-
introduceCheckBlockInVPlan(Plan, nullptr);
8069+
introduceCheckBlockInVPlan(Plan, Insert);
80728070
return Insert;
80738071
}
80748072

‎llvm/lib/Transforms/Vectorize/VPlan.cpp

Lines changed: 4 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -862,9 +862,8 @@ VPlanPtr VPlan::createInitialVPlan(Type *InductionTy,
862862
VPIRBasicBlock *Entry =
863863
VPIRBasicBlock::fromBasicBlock(TheLoop->getLoopPreheader());
864864
VPBasicBlock *VecPreheader = new VPBasicBlock("vector.ph");
865-
// Connect entry only to vector preheader initially. Edges to the scalar
866-
// preheader will be inserted later, during skeleton creation when runtime
867-
// guards are added as needed.
865+
// Connect entry only to vector preheader initially. Entry will also be connected to the scalar preheader later, during skeleton creation when runtime guards are added as needed.
866+
// Note that when executing the VPlan for an epilogue vector loop, the original entry block here will be replaced by a new VPIRBasicBlock wrapping the entry to the epilogue vector loop after generating code for the main vector loop.
868867
VPBlockUtils::connectBlocks(Entry, VecPreheader);
869868
VPIRBasicBlock *ScalarHeader =
870869
VPIRBasicBlock::fromBasicBlock(TheLoop->getHeader());
@@ -1021,12 +1020,11 @@ void VPlan::execute(VPTransformState *State) {
10211020
// blocks are created during skeleton creation, so we can only create the
10221021
// VPIRBasicBlocks now during VPlan execution rather than earlier during VPlan
10231022
// construction.
1024-
replaceVPBBWithIRVPBB(getVectorPreheader(), VectorPreHeader);
10251023
BasicBlock *MiddleBB = State->CFG.ExitBB;
10261024
BasicBlock *ScalarPh = MiddleBB->getSingleSuccessor();
1025+
replaceVPBBWithIRVPBB(getVectorPreheader(), VectorPreHeader);
1026+
replaceVPBBWithIRVPBB(getMiddleBlock(), MiddleBB);
10271027
replaceVPBBWithIRVPBB(getScalarPreheader(), ScalarPh);
1028-
VPBasicBlock *MiddleVPBB = getMiddleBlock();
1029-
replaceVPBBWithIRVPBB(MiddleVPBB, MiddleBB);
10301028

10311029
LLVM_DEBUG(dbgs() << "Executing best plan with VF=" << State->VF
10321030
<< ", UF=" << getUF() << '\n');

‎llvm/lib/Transforms/Vectorize/VPlan.h

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3844,8 +3844,8 @@ class VPlan {
38443844
}
38453845

38463846
/// Create initial VPlan, having an "entry" VPBasicBlock (wrapping
3847-
/// original scalar pre-header ) which contains SCEV expansions that need
3848-
/// to happen before the CFG is modified; a VPBasicBlock for the vector
3847+
/// original scalar pre-header) which contains SCEV expansions that need
3848+
/// to happen before the CFG is modified (when executing a VPlan for the epilogue vector loop, the original entry needs to be replaced by the new entry for the epilogue vector loop); a VPBasicBlock for the vector
38493849
/// pre-header, followed by a region for the vector loop, followed by the
38503850
/// middle VPBasicBlock. If a check is needed to guard executing the scalar
38513851
/// epilogue loop, it will be added to the middle block, together with

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3248,6 +3248,7 @@ void VPExpandSCEVRecipe::execute(VPTransformState &State) {
32483248

32493249
const DataLayout &DL = State.CFG.PrevBB->getDataLayout();
32503250
SCEVExpander Exp(SE, DL, "induction");
3251+
32513252
Value *Res = Exp.expandCodeFor(Expr, Expr->getType(),
32523253
&*State.Builder.GetInsertPoint());
32533254
State.ExpandedSCEVs[Expr] = Res;
@@ -3501,7 +3502,7 @@ void VPScalarPHIRecipe::execute(VPTransformState &State) {
35013502
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
35023503
void VPScalarPHIRecipe::print(raw_ostream &O, const Twine &Indent,
35033504
VPSlotTracker &SlotTracker) const {
3504-
O << Indent << "SCALAR-PHI";
3505+
O << Indent << "SCALAR-PHI ";
35053506
printAsOperand(O, SlotTracker);
35063507
O << " = phi ";
35073508
printOperands(O, SlotTracker);

‎llvm/lib/Transforms/Vectorize/VPlanVerifier.cpp

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -194,7 +194,6 @@ bool VPlanVerifier::verifyVPBasicBlock(const VPBasicBlock *VPBB) {
194194
errs() << "not in a VPIRBasicBlock!\n";
195195
return false;
196196
}
197-
198197
for (const VPValue *V : R.definedValues()) {
199198
for (const VPUser *U : V->users()) {
200199
auto *UI = dyn_cast<VPRecipeBase>(U);

‎llvm/test/Transforms/LoopVectorize/AArch64/extractvalue-no-scalarization-required.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -64,6 +64,7 @@ exit:
6464
declare float @powf(float, float) readnone nounwind
6565

6666
; Ensure the extractvalue + add instructions are hoisted out
67+
; CM-LABEL: Checking a loop in 'test_getVectorCallCost'
6768
; CM: vector.ph:
6869
; CM: CLONE ir<%a> = extractvalue ir<%sv>
6970
; CM: CLONE ir<%b> = extractvalue ir<%sv>

‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll

Lines changed: 169 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -144,6 +144,90 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
144144
; CHECK-NEXT: LEV: Epilogue vectorization is not profitable for this loop
145145
; CHECK: Executing best plan with VF=vscale x 4, UF=1
146146
; CHECK-NEXT: VPlan 'Final VPlan for VF={vscale x 4},UF={1}' {
147+
; CHECK-NEXT: Live-in ir<[[VF:%.+]]> = VF
148+
; CHECK-NEXT: Live-in ir<[[VFxUF:%.+]]>.1 = VF * UF
149+
; CHECK-NEXT: Live-in ir<[[VEC_TC:%.+]]> = vector-trip-count
150+
; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
151+
; CHECK-EMPTY:
152+
; CHECK-NEXT: ir-bb<for.body.preheader>:
153+
; CHECK-NEXT: IR %0 = zext i32 %n to i64
154+
; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (zext i32 %n to i64)
155+
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, ir-bb<vector.scevcheck>
156+
; CHECK-EMPTY:
157+
; CHECK-NEXT: ir-bb<vector.scevcheck>:
158+
; CHECK-NEXT: IR %3 = add nsw i64 %0, -1
159+
; CHECK-NEXT: IR %4 = add i32 %n, -1
160+
; CHECK-NEXT: IR %5 = trunc i64 %3 to i32
161+
; CHECK-NEXT: IR %mul = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 1, i32 %5)
162+
; CHECK-NEXT: IR %mul.result = extractvalue { i32, i1 } %mul, 0
163+
; CHECK-NEXT: IR %mul.overflow = extractvalue { i32, i1 } %mul, 1
164+
; CHECK-NEXT: IR %6 = sub i32 %4, %mul.result
165+
; CHECK-NEXT: IR %7 = icmp ugt i32 %6, %4
166+
; CHECK-NEXT: IR %8 = or i1 %7, %mul.overflow
167+
; CHECK-NEXT: IR %9 = icmp ugt i64 %3, 4294967295
168+
; CHECK-NEXT: IR %10 = or i1 %8, %9
169+
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, ir-bb<vector.memcheck>
170+
; CHECK-EMPTY:
171+
; CHECK-NEXT: ir-bb<vector.memcheck>:
172+
; CHECK-NEXT: IR %11 = call i64 @llvm.vscale.i64()
173+
; CHECK-NEXT: IR %12 = mul i64 %11, 4
174+
; CHECK-NEXT: IR %13 = mul i64 %12, 4
175+
; CHECK-NEXT: IR %14 = sub i64 %B1, %A2
176+
; CHECK-NEXT: IR %diff.check = icmp ult i64 %14, %13
177+
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, ir-bb<vector.ph>
178+
; CHECK-EMPTY:
179+
; CHECK-NEXT: ir-bb<vector.ph>:
180+
; CHECK-NEXT: IR %15 = call i64 @llvm.vscale.i64()
181+
; CHECK-NEXT: IR %16 = mul i64 %15, 4
182+
; CHECK-NEXT: IR %n.mod.vf = urem i64 %0, %16
183+
; CHECK-NEXT: IR %n.vec = sub i64 %0, %n.mod.vf
184+
; CHECK-NEXT: IR %ind.end = sub i64 %0, %n.vec
185+
; CHECK-NEXT: IR %.cast = trunc i64 %n.vec to i32
186+
; CHECK-NEXT: IR %ind.end3 = sub i32 %n, %.cast
187+
; CHECK-NEXT: IR %17 = call i64 @llvm.vscale.i64()
188+
; CHECK-NEXT: IR %18 = mul i64 %17, 4
189+
; CHECK-NEXT: Successor(s): vector loop
190+
; CHECK-EMPTY:
191+
; CHECK-NEXT: <x1> vector loop: {
192+
; CHECK-NEXT: vector.body:
193+
; CHECK-NEXT: SCALAR-PHI vp<[[CAN_IV:%.+]]> = phi ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
194+
; CHECK-NEXT: vp<[[DEV_IV:%.+]]> = DERIVED-IV ir<%n> + vp<[[CAN_IV]]> * ir<-1>
195+
; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[DEV_IV]]>, ir<-1>
196+
; CHECK-NEXT: CLONE ir<%i.0> = add nsw vp<[[STEPS]]>, ir<-1>
197+
; CHECK-NEXT: CLONE ir<%idxprom> = zext ir<%i.0>
198+
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%B>, ir<%idxprom>
199+
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx>, ir<[[VF]]>
200+
; CHECK-NEXT: WIDEN ir<[[L:%.+]]> = load vp<[[VEC_PTR]]>
201+
; CHECK-NEXT: WIDEN ir<%add9> = add ir<[[L]]>, ir<1>
202+
; CHECK-NEXT: CLONE ir<%arrayidx3> = getelementptr inbounds ir<%A>, ir<%idxprom>
203+
; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx3>, ir<[[VF]]>
204+
; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%add9>
205+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, ir<[[VFxUF]]>.1
206+
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, ir<[[VEC_TC]]>
207+
; CHECK-NEXT: No successors
208+
; CHECK-NEXT: }
209+
; CHECK-NEXT: Successor(s): ir-bb<middle.block>
210+
; CHECK-EMPTY:
211+
; CHECK-NEXT: ir-bb<middle.block>:
212+
; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq vp<[[TC]]>, ir<[[VEC_TC]]>
213+
; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]>
214+
; CHECK-NEXT: Successor(s): ir-bb<for.cond.cleanup.loopexit>, ir-bb<scalar.ph>
215+
; CHECK-EMPTY:
216+
; CHECK-NEXT: ir-bb<for.cond.cleanup.loopexit>:
217+
; CHECK-NEXT: No successors
218+
; CHECK-EMPTY:
219+
; CHECK-NEXT: ir-bb<scalar.ph>:
220+
; CHECK-NEXT: IR [[RESUME_1:%.+]] = phi i64
221+
; CHECK-NEXT: IR [[RESUME_2:%.+]] = phi i32
222+
; CHECK-NEXT: Successor(s): ir-bb<for.body>
223+
; CHECK-EMPTY:
224+
; CHECK-NEXT: ir-bb<for.body>:
225+
; CHECK-NEXT: IR %indvars.iv = phi i64 [ [[RESUME_1]], %scalar.ph ], [ %indvars.iv.next, %for.body ]
226+
; CHECK-NEXT: IR %i.0.in8 = phi i32 [ [[RESUME_2]], %scalar.ph ], [ %i.0, %for.body ]
227+
; CHECK: IR %indvars.iv.next = add nsw i64 %indvars.iv, -1
228+
; CHECK-NEXT: No successors
229+
; CHECK-NEXT: }
230+
; CHECK: LV: Loop does not require scalar epilogue
147231
;
148232
entry:
149233
%cmp7 = icmp sgt i32 %n, 0
@@ -306,6 +390,91 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
306390
; CHECK-NEXT: LV: Found a vectorizable loop (vscale x 4) in <stdin>
307391
; CHECK-NEXT: LEV: Epilogue vectorization is not profitable for this loop
308392
; CHECK: Executing best plan with VF=vscale x 4, UF=1
393+
; CHECK-NEXT: VPlan 'Final VPlan for VF={vscale x 4},UF={1}' {
394+
; CHECK-NEXT: Live-in ir<[[VF:%.+]]> = VF
395+
; CHECK-NEXT: Live-in ir<[[VFxUF:%.+]]>.1 = VF * UF
396+
; CHECK-NEXT: Live-in ir<[[VEC_TC:%.+]]> = vector-trip-count
397+
; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
398+
; CHECK-EMPTY:
399+
; CHECK-NEXT: ir-bb<for.body.preheader>:
400+
; CHECK-NEXT: IR %0 = zext i32 %n to i64
401+
; CHECK-NEXT: EMIT vp<[[TC]]> = EXPAND SCEV (zext i32 %n to i64)
402+
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, ir-bb<vector.scevcheck>
403+
; CHECK-EMPTY:
404+
; CHECK-NEXT: ir-bb<vector.scevcheck>:
405+
; CHECK-NEXT: IR %3 = add nsw i64 %0, -1
406+
; CHECK-NEXT: IR %4 = add i32 %n, -1
407+
; CHECK-NEXT: IR %5 = trunc i64 %3 to i32
408+
; CHECK-NEXT: IR %mul = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 1, i32 %5)
409+
; CHECK-NEXT: IR %mul.result = extractvalue { i32, i1 } %mul, 0
410+
; CHECK-NEXT: IR %mul.overflow = extractvalue { i32, i1 } %mul, 1
411+
; CHECK-NEXT: IR %6 = sub i32 %4, %mul.result
412+
; CHECK-NEXT: IR %7 = icmp ugt i32 %6, %4
413+
; CHECK-NEXT: IR %8 = or i1 %7, %mul.overflow
414+
; CHECK-NEXT: IR %9 = icmp ugt i64 %3, 4294967295
415+
; CHECK-NEXT: IR %10 = or i1 %8, %9
416+
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, ir-bb<vector.memcheck>
417+
; CHECK-EMPTY:
418+
; CHECK-NEXT: ir-bb<vector.memcheck>:
419+
; CHECK-NEXT: IR %11 = call i64 @llvm.vscale.i64()
420+
; CHECK-NEXT: IR %12 = mul i64 %11, 4
421+
; CHECK-NEXT: IR %13 = mul i64 %12, 4
422+
; CHECK-NEXT: IR %14 = sub i64 %B1, %A2
423+
; CHECK-NEXT: IR %diff.check = icmp ult i64 %14, %13
424+
; CHECK-NEXT: Successor(s): ir-bb<scalar.ph>, ir-bb<vector.ph>
425+
; CHECK-EMPTY:
426+
; CHECK-NEXT: ir-bb<vector.ph>:
427+
; CHECK-NEXT: IR %15 = call i64 @llvm.vscale.i64()
428+
; CHECK-NEXT: IR %16 = mul i64 %15, 4
429+
; CHECK-NEXT: IR %n.mod.vf = urem i64 %0, %16
430+
; CHECK-NEXT: IR %n.vec = sub i64 %0, %n.mod.vf
431+
; CHECK-NEXT: IR %ind.end = sub i64 %0, %n.vec
432+
; CHECK-NEXT: IR %.cast = trunc i64 %n.vec to i32
433+
; CHECK-NEXT: IR %ind.end3 = sub i32 %n, %.cast
434+
; CHECK-NEXT: IR %17 = call i64 @llvm.vscale.i64()
435+
; CHECK-NEXT: IR %18 = mul i64 %17, 4
436+
; CHECK-NEXT: Successor(s): vector loop
437+
; CHECK-EMPTY:
438+
; CHECK-NEXT: <x1> vector loop: {
439+
; CHECK-NEXT: vector.body:
440+
; CHECK-NEXT: SCALAR-PHI vp<[[CAN_IV:%.+]]> = phi ir<0>, vp<[[CAN_IV_NEXT:.+]]>
441+
; CHECK-NEXT: vp<[[DEV_IV:%.+]]> = DERIVED-IV ir<%n> + vp<[[CAN_IV]]> * ir<-1>
442+
; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[DEV_IV]]>, ir<-1>
443+
; CHECK-NEXT: CLONE ir<%i.0> = add nsw vp<[[STEPS]]>, ir<-1>
444+
; CHECK-NEXT: CLONE ir<%idxprom> = zext ir<%i.0>
445+
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%B>, ir<%idxprom>
446+
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx>, ir<[[VF]]>
447+
; CHECK-NEXT: WIDEN ir<[[L:%.+]]> = load vp<[[VEC_PTR]]>
448+
; CHECK-NEXT: WIDEN ir<%conv1> = fadd ir<[[L]]>, ir<1.000000e+00>
449+
; CHECK-NEXT: CLONE ir<%arrayidx3> = getelementptr inbounds ir<%A>, ir<%idxprom>
450+
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx3>, ir<[[VF]]>
451+
; CHECK-NEXT: WIDEN store vp<[[VEC_PTR]]>, ir<%conv1>
452+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, ir<[[VFxUF]]>.1
453+
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, ir<[[VEC_TC]]>
454+
; CHECK-NEXT: No successors
455+
; CHECK-NEXT: }
456+
; CHECK-NEXT: Successor(s): ir-bb<middle.block>
457+
; CHECK-EMPTY:
458+
; CHECK-NEXT: ir-bb<middle.block>:
459+
; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq vp<[[TC]]>, ir<[[VEC_TC]]>
460+
; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]>
461+
; CHECK-NEXT: Successor(s): ir-bb<for.cond.cleanup.loopexit>, ir-bb<scalar.ph>
462+
; CHECK-EMPTY:
463+
; CHECK-NEXT: ir-bb<for.cond.cleanup.loopexit>:
464+
; CHECK-NEXT: No successors
465+
; CHECK-EMPTY:
466+
; CHECK-NEXT: ir-bb<scalar.ph>:
467+
; CHECK-NEXT: IR [[RESUME_1:%.+]] = phi i64
468+
; CHECK-NEXT: IR [[RESUME_2:%.+]] = phi i32
469+
; CHECK-NEXT: Successor(s): ir-bb<for.body>
470+
; CHECK-EMPTY:
471+
; CHECK-NEXT: ir-bb<for.body>:
472+
; CHECK-NEXT: IR %indvars.iv = phi i64 [ [[RESUME_1]], %scalar.ph ], [ %indvars.iv.next, %for.body ]
473+
; CHECK-NEXT: IR %i.0.in8 = phi i32 [ [[RESUME_2]], %scalar.ph ], [ %i.0, %for.body ]
474+
; CHECK: IR %indvars.iv.next = add nsw i64 %indvars.iv, -1
475+
; CHECK-NEXT: No successors
476+
; CHECK-NEXT: }
477+
; CHECK: LV: Loop does not require scalar epilogue
309478
;
310479
entry:
311480
%cmp7 = icmp sgt i32 %n, 0

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,8 @@
2727

2828
; IF-EVL: <x1> vector loop: {
2929
; IF-EVL-NEXT: vector.body:
30-
; IF-EVL-NEXT: EMIT vp<[[IV:%[0-9]+]]> = CANONICAL-INDUCTION
31-
; IF-EVL-NEXT: EXPLICIT-VECTOR-LENGTH-BASED-IV-PHI vp<[[EVL_PHI:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEX:%.+]]>
30+
; IF-EVL-NEXT: SCALAR-PHI vp<[[IV:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEXT_EXIT:%.+]]>
31+
; IF-EVL-NEXT: SCALAR-PHI vp<[[EVL_PHI:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEX:%.+]]>
3232
; IF-EVL-NEXT: EMIT vp<[[AVL:%.+]]> = sub ir<%N>, vp<[[EVL_PHI]]>
3333
; IF-EVL-NEXT: EMIT vp<[[EVL:%.+]]> = EXPLICIT-VECTOR-LENGTH vp<[[AVL]]>
3434
; IF-EVL-NEXT: vp<[[ST:%[0-9]+]]> = SCALAR-STEPS vp<[[EVL_PHI]]>, ir<1>
@@ -47,7 +47,7 @@
4747
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR3]]>, ir<[[ADD]]>, vp<[[EVL]]>
4848
; IF-EVL-NEXT: SCALAR-CAST vp<[[CAST:%[0-9]+]]> = zext vp<[[EVL]]> to i64
4949
; IF-EVL-NEXT: EMIT vp<[[IV_NEX]]> = add vp<[[CAST]]>, vp<[[EVL_PHI]]>
50-
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT_EXIT:%.+]]> = add vp<[[IV]]>, ir<%8>
50+
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT_EXIT]]> = add vp<[[IV]]>, ir<%8>
5151
; IF-EVL-NEXT: EMIT branch-on-count vp<[[IV_NEXT_EXIT]]>, ir<%n.vec>
5252
; IF-EVL-NEXT: No successors
5353
; IF-EVL-NEXT: }

‎llvm/test/Transforms/LoopVectorize/vplan-predicate-switch.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -19,7 +19,7 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
1919
; CHECK-EMPTY:
2020
; CHECK-NEXT: <x1> vector loop: {
2121
; CHECK-NEXT: vector.body:
22-
; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
22+
; CHECK-NEXT: SCALAR-PHI vp<[[CAN_IV:%.+]]> = phi ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
2323
; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
2424
; CHECK-NEXT: EMIT vp<[[PTR:%.+]]> = ptradd ir<%start>, vp<[[STEPS]]>
2525
; CHECK-NEXT: vp<[[WIDE_PTR:%.+]]> = vector-pointer vp<[[PTR]]>

‎llvm/test/Transforms/LoopVectorize/vplan-printing.ll

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -505,6 +505,7 @@ define float @print_fmuladd_strict(ptr %a, ptr %b, i64 %n) {
505505
; CHECK-EMPTY:
506506
; CHECK-NEXT: ir-bb<for.end>
507507
; CHECK-NEXT: IR %muladd.lcssa = phi float [ %muladd, %for.body ] (extra operand: vp<[[RED_EX]]> from middle.block)
508+
; CHECK-NEXT: No successors
508509
; CHECK-NEXT:}
509510

510511
entry:

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