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[ELF] Pass Ctx & to read32/write32
1 parent c1b206f commit 38dfcd9

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11 files changed

+367
-351
lines changed

11 files changed

+367
-351
lines changed

‎lld/ELF/Arch/AArch64.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -265,7 +265,7 @@ int64_t AArch64::getImplicitAddend(const uint8_t *buf, RelType type) const {
265265
return SignExtend64<16>(read16(buf));
266266
case R_AARCH64_ABS32:
267267
case R_AARCH64_PREL32:
268-
return SignExtend64<32>(read32(buf));
268+
return SignExtend64<32>(read32(ctx, buf));
269269
case R_AARCH64_ABS64:
270270
case R_AARCH64_PREL64:
271271
case R_AARCH64_RELATIVE:
@@ -490,12 +490,12 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
490490
case R_AARCH64_ABS32:
491491
case R_AARCH64_PREL32:
492492
checkIntUInt(loc, val, 32, rel);
493-
write32(loc, val);
493+
write32(ctx, loc, val);
494494
break;
495495
case R_AARCH64_PLT32:
496496
case R_AARCH64_GOTPCREL32:
497497
checkInt(loc, val, 32, rel);
498-
write32(loc, val);
498+
write32(ctx, loc, val);
499499
break;
500500
case R_AARCH64_ABS64:
501501
// AArch64 relocations to tagged symbols have extended semantics, as
@@ -526,7 +526,7 @@ void AArch64::relocate(uint8_t *loc, const Relocation &rel,
526526
// finalizeAddressDependentContent(). Writing the value is harmless
527527
// because dynamic linking ignores it.
528528
if (isInt<32>(val))
529-
write32(loc, val);
529+
write32(ctx, loc, val);
530530
break;
531531
case R_AARCH64_ADD_ABS_LO12_NC:
532532
write32Imm12(loc, val);

‎lld/ELF/Arch/ARM.cpp

Lines changed: 57 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -208,28 +208,28 @@ RelType ARM::getDynRel(RelType type) const {
208208
}
209209

210210
void ARM::writeGotPlt(uint8_t *buf, const Symbol &) const {
211-
write32(buf, ctx.in.plt->getVA());
211+
write32(ctx, buf, ctx.in.plt->getVA());
212212
}
213213

214214
void ARM::writeIgotPlt(uint8_t *buf, const Symbol &s) const {
215215
// An ARM entry is the address of the ifunc resolver function.
216-
write32(buf, s.getVA());
216+
write32(ctx, buf, s.getVA());
217217
}
218218

219219
// Long form PLT Header that does not have any restrictions on the displacement
220220
// of the .plt from the .got.plt.
221221
static void writePltHeaderLong(Ctx &ctx, uint8_t *buf) {
222-
write32(buf + 0, 0xe52de004); // str lr, [sp,#-4]!
223-
write32(buf + 4, 0xe59fe004); // ldr lr, L2
224-
write32(buf + 8, 0xe08fe00e); // L1: add lr, pc, lr
225-
write32(buf + 12, 0xe5bef008); // ldr pc, [lr, #8]
226-
write32(buf + 16, 0x00000000); // L2: .word &(.got.plt) - L1 - 8
227-
write32(buf + 20, 0xd4d4d4d4); // Pad to 32-byte boundary
228-
write32(buf + 24, 0xd4d4d4d4); // Pad to 32-byte boundary
229-
write32(buf + 28, 0xd4d4d4d4);
222+
write32(ctx, buf + 0, 0xe52de004); // str lr, [sp,#-4]!
223+
write32(ctx, buf + 4, 0xe59fe004); // ldr lr, L2
224+
write32(ctx, buf + 8, 0xe08fe00e); // L1: add lr, pc, lr
225+
write32(ctx, buf + 12, 0xe5bef008); // ldr pc, [lr, #8]
226+
write32(ctx, buf + 16, 0x00000000); // L2: .word &(.got.plt) - L1 - 8
227+
write32(ctx, buf + 20, 0xd4d4d4d4); // Pad to 32-byte boundary
228+
write32(ctx, buf + 24, 0xd4d4d4d4); // Pad to 32-byte boundary
229+
write32(ctx, buf + 28, 0xd4d4d4d4);
230230
uint64_t gotPlt = ctx.in.gotPlt->getVA();
231231
uint64_t l1 = ctx.in.plt->getVA() + 8;
232-
write32(buf + 16, gotPlt - l1 - 8);
232+
write32(ctx, buf + 16, gotPlt - l1 - 8);
233233
}
234234

235235
// True if we should use Thumb PLTs, which currently require Thumb2, and are
@@ -263,7 +263,7 @@ void ARM::writePltHeader(uint8_t *buf) const {
263263
// Split into two halves to support endianness correctly.
264264
write16(buf + 8, 0xf85e);
265265
write16(buf + 10, 0xff08);
266-
write32(buf + 12, offset);
266+
write32(ctx, buf + 12, offset);
267267

268268
memcpy(buf + 16, trapInstr.data(), 4); // Pad to 32-byte boundary
269269
memcpy(buf + 20, trapInstr.data(), 4);
@@ -287,10 +287,10 @@ void ARM::writePltHeader(uint8_t *buf) const {
287287
writePltHeaderLong(ctx, buf);
288288
return;
289289
}
290-
write32(buf + 0, pltData[0]);
291-
write32(buf + 4, pltData[1] | ((offset >> 20) & 0xff));
292-
write32(buf + 8, pltData[2] | ((offset >> 12) & 0xff));
293-
write32(buf + 12, pltData[3] | (offset & 0xfff));
290+
write32(ctx, buf + 0, pltData[0]);
291+
write32(ctx, buf + 4, pltData[1] | ((offset >> 20) & 0xff));
292+
write32(ctx, buf + 8, pltData[2] | ((offset >> 12) & 0xff));
293+
write32(ctx, buf + 12, pltData[3] | (offset & 0xfff));
294294
memcpy(buf + 16, trapInstr.data(), 4); // Pad to 32-byte boundary
295295
memcpy(buf + 20, trapInstr.data(), 4);
296296
memcpy(buf + 24, trapInstr.data(), 4);
@@ -312,12 +312,12 @@ void ARM::addPltHeaderSymbols(InputSection &isec) const {
312312
// of the .plt from the .got.plt.
313313
static void writePltLong(uint8_t *buf, uint64_t gotPltEntryAddr,
314314
uint64_t pltEntryAddr) {
315-
write32(buf + 0, 0xe59fc004); // ldr ip, L2
316-
write32(buf + 4, 0xe08cc00f); // L1: add ip, ip, pc
317-
write32(buf + 8, 0xe59cf000); // ldr pc, [ip]
318-
write32(buf + 12, 0x00000000); // L2: .word Offset(&(.got.plt) - L1 - 8
315+
write32(ctx, buf + 0, 0xe59fc004); // ldr ip, L2
316+
write32(ctx, buf + 4, 0xe08cc00f); // L1: add ip, ip, pc
317+
write32(ctx, buf + 8, 0xe59cf000); // ldr pc, [ip]
318+
write32(ctx, buf + 12, 0x00000000); // L2: .word Offset(&(.got.plt) - L1 - 8
319319
uint64_t l1 = pltEntryAddr + 4;
320-
write32(buf + 12, gotPltEntryAddr - l1 - 8);
320+
write32(ctx, buf + 12, gotPltEntryAddr - l1 - 8);
321321
}
322322

323323
// The default PLT entries require the .got.plt to be within 128 Mb of the
@@ -342,9 +342,9 @@ void ARM::writePlt(uint8_t *buf, const Symbol &sym,
342342
writePltLong(buf, sym.getGotPltVA(ctx), pltEntryAddr);
343343
return;
344344
}
345-
write32(buf + 0, pltData[0] | ((offset >> 20) & 0xff));
346-
write32(buf + 4, pltData[1] | ((offset >> 12) & 0xff));
347-
write32(buf + 8, pltData[2] | (offset & 0xfff));
345+
write32(ctx, buf + 0, pltData[0] | ((offset >> 20) & 0xff));
346+
write32(ctx, buf + 4, pltData[1] | ((offset >> 12) & 0xff));
347+
write32(ctx, buf + 8, pltData[2] | (offset & 0xfff));
348348
memcpy(buf + 12, trapInstr.data(), 4); // Pad to 16-byte boundary
349349
} else {
350350
uint64_t offset = sym.getGotPltVA(ctx) - pltEntryAddr - 12;
@@ -558,7 +558,8 @@ void ARM::encodeAluGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
558558
if (check && imm > 0xff)
559559
error(getErrorLoc(ctx, loc) + "unencodeable immediate " + Twine(val).str() +
560560
" for relocation " + toString(rel.type));
561-
write32(loc, (read32(loc) & 0xff3ff000) | opcode | rot | (imm & 0xff));
561+
write32(ctx, loc,
562+
(read32(ctx, loc) & 0xff3ff000) | opcode | rot | (imm & 0xff));
562563
}
563564

564565
static void encodeLdrGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
@@ -576,7 +577,7 @@ static void encodeLdrGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
576577
}
577578
uint32_t imm = getRemAndLZForGroup(group, val).first;
578579
checkUInt(loc, imm, 12, rel);
579-
write32(loc, (read32(loc) & 0xff7ff000) | opcode | imm);
580+
write32(ctx, loc, (read32(ctx, loc) & 0xff7ff000) | opcode | imm);
580581
}
581582

582583
static void encodeLdrsGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
@@ -594,8 +595,9 @@ static void encodeLdrsGroup(uint8_t *loc, const Relocation &rel, uint64_t val,
594595
}
595596
uint32_t imm = getRemAndLZForGroup(group, val).first;
596597
checkUInt(loc, imm, 8, rel);
597-
write32(loc, (read32(loc) & 0xff7ff0f0) | opcode | ((imm & 0xf0) << 4) |
598-
(imm & 0xf));
598+
write32(ctx, loc,
599+
(read32(ctx, loc) & 0xff7ff0f0) | opcode | ((imm & 0xf0) << 4) |
600+
(imm & 0xf));
599601
}
600602

601603
void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
@@ -617,11 +619,11 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
617619
case R_ARM_TLS_LE32:
618620
case R_ARM_TLS_TPOFF32:
619621
case R_ARM_TLS_DTPOFF32:
620-
write32(loc, val);
622+
write32(ctx, loc, val);
621623
break;
622624
case R_ARM_PREL31:
623625
checkInt(loc, val, 31, rel);
624-
write32(loc, (read32(loc) & 0x80000000) | (val & ~0x80000000));
626+
write32(ctx, loc, (read32(ctx, loc) & 0x80000000) | (val & ~0x80000000));
625627
break;
626628
case R_ARM_CALL: {
627629
// R_ARM_CALL is used for BL and BLX instructions, for symbols of type
@@ -630,40 +632,42 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
630632
// not of type STT_FUNC then we must preserve the original instruction.
631633
assert(rel.sym); // R_ARM_CALL is always reached via relocate().
632634
bool bit0Thumb = val & 1;
633-
bool isBlx = (read32(loc) & 0xfe000000) == 0xfa000000;
635+
bool isBlx = (read32(ctx, loc) & 0xfe000000) == 0xfa000000;
634636
// lld 10.0 and before always used bit0Thumb when deciding to write a BLX
635637
// even when type not STT_FUNC.
636638
if (!rel.sym->isFunc() && isBlx != bit0Thumb)
637639
stateChangeWarning(ctx, loc, rel.type, *rel.sym);
638640
if (rel.sym->isFunc() ? bit0Thumb : isBlx) {
639641
// The BLX encoding is 0xfa:H:imm24 where Val = imm24:H:'1'
640642
checkInt(loc, val, 26, rel);
641-
write32(loc, 0xfa000000 | // opcode
642-
((val & 2) << 23) | // H
643-
((val >> 2) & 0x00ffffff)); // imm24
643+
write32(ctx, loc,
644+
0xfa000000 | // opcode
645+
((val & 2) << 23) | // H
646+
((val >> 2) & 0x00ffffff)); // imm24
644647
break;
645648
}
646649
// BLX (always unconditional) instruction to an ARM Target, select an
647650
// unconditional BL.
648-
write32(loc, 0xeb000000 | (read32(loc) & 0x00ffffff));
651+
write32(ctx, loc, 0xeb000000 | (read32(ctx, loc) & 0x00ffffff));
649652
// fall through as BL encoding is shared with B
650653
}
651654
[[fallthrough]];
652655
case R_ARM_JUMP24:
653656
case R_ARM_PC24:
654657
case R_ARM_PLT32:
655658
checkInt(loc, val, 26, rel);
656-
write32(loc, (read32(loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff));
659+
write32(ctx, loc,
660+
(read32(ctx, loc) & ~0x00ffffff) | ((val >> 2) & 0x00ffffff));
657661
break;
658662
case R_ARM_THM_JUMP8:
659663
// We do a 9 bit check because val is right-shifted by 1 bit.
660664
checkInt(loc, val, 9, rel);
661-
write16(loc, (read32(loc) & 0xff00) | ((val >> 1) & 0x00ff));
665+
write16(loc, (read32(ctx, loc) & 0xff00) | ((val >> 1) & 0x00ff));
662666
break;
663667
case R_ARM_THM_JUMP11:
664668
// We do a 12 bit check because val is right-shifted by 1 bit.
665669
checkInt(loc, val, 12, rel);
666-
write16(loc, (read32(loc) & 0xf800) | ((val >> 1) & 0x07ff));
670+
write16(loc, (read32(ctx, loc) & 0xf800) | ((val >> 1) & 0x07ff));
667671
break;
668672
case R_ARM_THM_JUMP19:
669673
// Encoding T3: Val = S:J2:J1:imm6:imm11:0
@@ -733,14 +737,16 @@ void ARM::relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const {
733737
case R_ARM_MOVW_ABS_NC:
734738
case R_ARM_MOVW_PREL_NC:
735739
case R_ARM_MOVW_BREL_NC:
736-
write32(loc, (read32(loc) & ~0x000f0fff) | ((val & 0xf000) << 4) |
737-
(val & 0x0fff));
740+
write32(ctx, loc,
741+
(read32(ctx, loc) & ~0x000f0fff) | ((val & 0xf000) << 4) |
742+
(val & 0x0fff));
738743
break;
739744
case R_ARM_MOVT_ABS:
740745
case R_ARM_MOVT_PREL:
741746
case R_ARM_MOVT_BREL:
742-
write32(loc, (read32(loc) & ~0x000f0fff) |
743-
(((val >> 16) & 0xf000) << 4) | ((val >> 16) & 0xfff));
747+
write32(ctx, loc,
748+
(read32(ctx, loc) & ~0x000f0fff) | (((val >> 16) & 0xf000) << 4) |
749+
((val >> 16) & 0xfff));
744750
break;
745751
case R_ARM_THM_MOVT_ABS:
746752
case R_ARM_THM_MOVT_PREL:
@@ -890,14 +896,14 @@ int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const {
890896
case R_ARM_TLS_LE32:
891897
case R_ARM_TLS_LDO32:
892898
case R_ARM_TLS_TPOFF32:
893-
return SignExtend64<32>(read32(buf));
899+
return SignExtend64<32>(read32(ctx, buf));
894900
case R_ARM_PREL31:
895-
return SignExtend64<31>(read32(buf));
901+
return SignExtend64<31>(read32(ctx, buf));
896902
case R_ARM_CALL:
897903
case R_ARM_JUMP24:
898904
case R_ARM_PC24:
899905
case R_ARM_PLT32:
900-
return SignExtend64<26>(read32(buf) << 2);
906+
return SignExtend64<26>(read32(ctx, buf) << 2);
901907
case R_ARM_THM_JUMP8:
902908
return SignExtend64<9>(read16(buf) << 1);
903909
case R_ARM_THM_JUMP11:
@@ -942,7 +948,7 @@ int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const {
942948
case R_ARM_MOVT_PREL:
943949
case R_ARM_MOVW_BREL_NC:
944950
case R_ARM_MOVT_BREL: {
945-
uint64_t val = read32(buf) & 0x000f0fff;
951+
uint64_t val = read32(ctx, buf) & 0x000f0fff;
946952
return SignExtend64<16>(((val & 0x000f0000) >> 4) | (val & 0x00fff));
947953
}
948954
case R_ARM_THM_MOVW_ABS_NC:
@@ -973,7 +979,7 @@ int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const {
973979
// right rotation and 8-bit constant. After the rotation the value
974980
// is zero-extended. When bit 23 is set the instruction is an add, when
975981
// bit 22 is set it is a sub.
976-
uint32_t instr = read32(buf);
982+
uint32_t instr = read32(ctx, buf);
977983
uint32_t val = rotr32(instr & 0xff, ((instr & 0xf00) >> 8) * 2);
978984
return (instr & 0x00400000) ? -val : val;
979985
}
@@ -982,15 +988,15 @@ int64_t ARM::getImplicitAddend(const uint8_t *buf, RelType type) const {
982988
case R_ARM_LDR_PC_G2: {
983989
// ADR (literal) add = bit23, sub = bit22
984990
// LDR (literal) u = bit23 unsigned imm12
985-
bool u = read32(buf) & 0x00800000;
986-
uint32_t imm12 = read32(buf) & 0xfff;
991+
bool u = read32(ctx, buf) & 0x00800000;
992+
uint32_t imm12 = read32(ctx, buf) & 0xfff;
987993
return u ? imm12 : -imm12;
988994
}
989995
case R_ARM_LDRS_PC_G0:
990996
case R_ARM_LDRS_PC_G1:
991997
case R_ARM_LDRS_PC_G2: {
992998
// LDRD/LDRH/LDRSB/LDRSH (literal) u = bit23 unsigned imm8
993-
uint32_t opcode = read32(buf);
999+
uint32_t opcode = read32(ctx, buf);
9941000
bool u = opcode & 0x00800000;
9951001
uint32_t imm4l = opcode & 0xf;
9961002
uint32_t imm4h = (opcode & 0xf00) >> 4;
@@ -1089,7 +1095,7 @@ static void toLittleEndianInstructions(uint8_t *buf, uint64_t start,
10891095
CodeState curState = static_cast<CodeState>(width);
10901096
if (curState == CodeState::Arm)
10911097
for (uint64_t i = start; i < end; i += width)
1092-
write32le(buf + i, read32(buf + i));
1098+
write32le(buf + i, read32(ctx, buf + i));
10931099

10941100
if (curState == CodeState::Thumb)
10951101
for (uint64_t i = start; i < end; i += width)

‎lld/ELF/Arch/Hexagon.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -410,7 +410,7 @@ int64_t Hexagon::getImplicitAddend(const uint8_t *buf, RelType type) const {
410410
case R_HEX_DTPMOD_32:
411411
case R_HEX_DTPREL_32:
412412
case R_HEX_TPREL_32:
413-
return SignExtend64<32>(read32(buf));
413+
return SignExtend64<32>(read32(ctx, buf));
414414
default:
415415
internalLinkerError(getErrorLoc(ctx, buf),
416416
"cannot read addend for relocation " + toString(type));

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